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I think I found a possible cause for the problem. I am using Modelsim Starter Edition, my surrounding code is in VHDL, while the code generated by Qsys is in verilog. The Starter Edition for what I´ve seen does not support mixed-language simulation, so this may well be at the root of the problem. Does anyone know whether it is possible to generate the tempcalc_onchip_memory2.0.v and the functions used in it in VDHL instead of verilog? Choosing to create HDL design files for synthesis does not change this generated file.
UPDATE:
I have recreated my surrounding modules in verilog(there are some decent VHDL->verilog converters online, I chose vhd2vl), and run the simulation with those, generating the whole qsys module in verilog too. The simulation works without a problem now.
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To fix this issue the "altera_mf_ver" library must be called before the "altera_mf" library.
For example
vsim -t ps -novopt -L altera_mf_ver -L altera_mf
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