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Altera_Forum
Honored Contributor
Honored ContributorDual-port access avalon memory simulation problem
Hello, I have created an Avalon dual access on-chip memory in Qsys and tried to simulate it, with success, everything worked just fine. Then I put this module in a VHDL component, and did nothi...
Altera_ForumHonored Contributor
Honored ContributorThe error messages indicate "missing Verilog connection for formal VHDL port." Are you missing some connections? What does the code to instantiate this look like?
