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KJ's avatar
KJ
Icon for New Contributor rankNew Contributor
9 days ago

Agilex 5: Cascading DSPs in tensor-mode doesn't work

Hi,

In my design for Agilex 5 I have two DSPs, configured in tensor fixed-point mode with side feed control, cascaded together. I expect the summation of the dot products in the second (last-in-chain) DSP to include the result from the previous (first-in-chain) DSP.

This works in simulation using the simulation models generated by the IP generator (which are based on tenm_dsp_prime primitives), and the Technology Map Viewer shows that the cascade connection is present in the placed-and-routed design.

The issue is that it doesn't work once programmed on the FPGA. The summation of the dot products in both DSPs works in each of them separately, but the second (last-in-chain) DSP doesn't include the cascade output from the first DSP. This has been confirmed with SignalTap, i.e., I can see that the dot-product summation outputs (FXP32) correctly reflect the result of the dot-product summation for their respective inputs, but the second DSP doesn't include the cascaded result. The cascaded path cannot be tapped.

Both DSPs were generated with IP generator with the following settings:

* DSP 1 (first-in-chain): cascade_in = disabled (ZERO_TENSOR_CHAIN_OUTPUT set in .ip file), cascade_out = enabled

* DSP 2 (last-in-chain) : cascade_in = enabled (TENSOR_CHAIN_OUTPUT set in .ip file), cascade_out = disabled

My suspicion is that the input multiplexer in the last-in-chain DSP is somehow not set correctly to include the cascaded path, despite correct settings in the .ip file.

Here are the details of my setup:

* dev kit: Agilex 5E065B Premium DK

* tools : Quartus Prime 25.3.1 build 100 12/19/2025 SC Pro Edition + 1.02 patch

* os : Ubuntu 24.04.3 LTS

I'd like to confirm whether it's a known issue with the cascade multiplexer configuration or whether some additional constraints are needed to make sure the cascaded path is correctly enabled.

Can you provide a resolution to this issue?

Thanks,

KJ

 

Programmable Logic Device

3 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    2 hours ago

    Hi,

     

    Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible. 

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    1 hour ago

    Hi,

     

    As I understand, you have questions regarding the Agilex DSP behavior, where the observed output does not match your expectations. To ensure we are aligned and to help me better understand the issue, could you please assist with the following:

     

    Simulation case
    Please share a simple test design and simulation setup, with steps to replicate the simulation, along with a brief description or illustration of the expected behavior.

     

    Hardware reproduction
    Please also share a minimal hardware test design that can reproduce the issue, together with steps to replicate and SignalTap captures highlighting the unexpected behavior.

     

    This information will help me better understand the DSP IP configuration, test setup, and observed behavior, and will greatly facilitate further debugging.

     

    Please feel free to let me know if you have any questions or need clarification. Thank you.

  • KJ's avatar
    KJ
    Icon for New Contributor rankNew Contributor
    33 minutes ago

    Hi,

    Thank you for your response.

    Is there a way to reach you directly? Could you provide an e-mail address?

    Many thanks,

    Chris