Dual-port access avalon memory simulation problem

The code for my testbench is:

LIBRARY altera_mf ;

LIBRARY ieee ;

LIBRARY std ;

USE altera_mf.all ;

USE ieee.std_logic_1164.all ;

USE ieee.std_logic_textio.all ;

USE ieee.std_logic_unsigned.all ;

use ieee.numeric_std.all;

USE std.textio.all ;

ENTITY tau2_temp_calculate_tb IS

END ;

ARCHITECTURE tau2_temp_calculate_tb_arch OF tau2_temp_calculate_tb IS

SIGNAL onchip_memory2_0_clk1_clk : STD_LOGIC;

SIGNAL onchip_memory2_0_s1_address : STD_LOGIC_VECTOR(13 DOWNTO 0);

SIGNAL onchip_memory2_0_s1_readdata : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL onchip_memory2_0_clk2_clk : std_logic;

SIGNAL onchip_memory2_0_reset2_reset : std_logic;

SIGNAL onchip_memory2_0_s2_address : std_logic_vector(13 downto 0);

SIGNAL onchip_memory2_0_s2_chipselect : std_logic;

SIGNAL onchip_memory2_0_s2_clken : std_logic;

SIGNAL onchip_memory2_0_s2_write : std_logic;

SIGNAL onchip_memory2_0_s2_readdata : std_logic_vector(31 downto 0);

SIGNAL onchip_memory2_0_s2_writedata : std_logic_vector(31 downto 0);

SIGNAL onchip_memory2_0_s2_byteenable : std_logic_vector(3 downto 0);

SIGNAL onchip_memory2_0_reset1_reset : std_logic;

SIGNAL onchip_memory2_0_s1_clken : std_logic;

SIGNAL onchip_memory2_0_s1_chipselect : std_logic;

SIGNAL onchip_memory2_0_s1_write : std_logic;

SIGNAL onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0);

SIGNAL onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0);

COMPONENT tau2_temp_calculate

PORT(

onchip_memory2_0_clk1_clk : IN STD_LOGIC;

onchip_memory2_0_s1_address : IN STD_LOGIC_VECTOR(13 DOWNTO 0);

onchip_memory2_0_s1_readdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

onchip_memory2_0_clk2_clk : in std_logic;

onchip_memory2_0_reset2_reset : in std_logic; -- onchip_memory2_0_reset2.reset

onchip_memory2_0_s2_address : in std_logic_vector(13 downto 0); -- onchip_memory2_0_s2.address

onchip_memory2_0_s2_chipselect : in std_logic; -- .chipselect

onchip_memory2_0_s2_clken : in std_logic; -- .clken

onchip_memory2_0_s2_write : in std_logic; -- .write

onchip_memory2_0_s2_readdata : out std_logic_vector(31 downto 0); -- .readdata

onchip_memory2_0_s2_writedata : in std_logic_vector(31 downto 0); -- .writedata

onchip_memory2_0_s2_byteenable : in std_logic_vector(3 downto 0);

onchip_memory2_0_reset1_reset : in std_logic;

onchip_memory2_0_s1_clken : in std_logic;

onchip_memory2_0_s1_chipselect : in std_logic;

onchip_memory2_0_s1_write : in std_logic;

onchip_memory2_0_s1_writedata : in std_logic_vector(31 downto 0);

onchip_memory2_0_s1_byteenable : in std_logic_vector(3 downto 0)

);

END COMPONENT;

BEGIN

tau2_temp_calculate_inst: tau2_temp_calculate

PORT MAP(

onchip_memory2_0_clk1_clk =>onchip_memory2_0_clk1_clk,

onchip_memory2_0_s1_address =>onchip_memory2_0_s1_address,

onchip_memory2_0_clk2_clk =>'0',

onchip_memory2_0_reset2_reset=>'0',

onchip_memory2_0_s2_address=>(others => '0'),

onchip_memory2_0_s2_chipselect=>'0',

onchip_memory2_0_s2_clken=>'0',

onchip_memory2_0_s2_write=>'0',

onchip_memory2_0_s2_readdata=>onchip_memory2_0_s2_readdata,

onchip_memory2_0_s2_writedata=>(others => '0'),

onchip_memory2_0_s2_byteenable=>(others => '0'),

onchip_memory2_0_reset1_reset=>'0',

onchip_memory2_0_s1_clken => '1',

onchip_memory2_0_s1_chipselect=> '1',

onchip_memory2_0_s1_write => '0',

onchip_memory2_0_s1_writedata => "00000000000000000000000000000000",

onchip_memory2_0_s1_byteenable=> (others => '1')

);

Process

variable DataIN : unsigned(13 downto 0);

Begin

DataIN:=to_unsigned(0,DataIN'length);

for Z in 1 to 16383

loop

onchip_memory2_0_s1_address <= std_logic_vector(DataIN) ;

wait for 47532 ps;

DataIN:=DataIN+to_unsigned(1,DataIN'length);

end loop;

wait;

End Process;

Process

Begin

for Z in 1 to 16383

loop

onchip_memory2_0_clk1_clk <= '1' ;

wait for 23766 ps ; --"1" period:1/2*(10^12/147.27*10^6)

onchip_memory2_0_clk1_clk <= '0' ;

wait for 23766 ps ; --"0" period:1/2*(10^12/147.27*10^6)

end loop;

wait;

End Process;

END;