Dual-port access avalon memory simulation problem

Hello,

Thank you for your reply, you can find the code to instantiate the component below. I do not think I left anything unconnected, as you can see on the picture attached(I unchecked the reset request option on generation).

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY tau2_temp_calculate IS

PORT( onchip_memory2_0_clk1_clk : IN STD_LOGIC;

onchip_memory2_0_s1_address : IN STD_LOGIC_VECTOR(13 DOWNTO 0);

onchip_memory2_0_s1_readdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

onchip_memory2_0_clk2_clk : in std_logic;

onchip_memory2_0_reset2_reset : in std_logic; -- onchip_memory2_0_reset2.reset

onchip_memory2_0_s2_address : in std_logic_vector(13 downto 0); -- onchip_memory2_0_s2.address

onchip_memory2_0_s2_chipselect : in std_logic; -- .chipselect

onchip_memory2_0_s2_clken : in std_logic; -- .clken

onchip_memory2_0_s2_write : in std_logic; -- .write

onchip_memory2_0_s2_readdata : out std_logic_vector(31 downto 0); -- .readdata

onchip_memory2_0_s2_writedata : in std_logic_vector(31 downto 0); -- .writedata

onchip_memory2_0_s2_byteenable : in std_logic_vector(3 downto 0);

onchip_memory2_0_reset1_reset : in std_logic;

onchip_memory2_0_s1_clken : in std_logic;

onchip_memory2_0_s1_chipselect : in std_logic;

onchip_memory2_0_s1_write : in std_logic;

onchip_memory2_0_s1_writedata : in std_logic_vector(31 downto 0);

onchip_memory2_0_s1_byteenable : in std_logic_vector(3 downto 0)

);

END tau2_temp_calculate;

ARCHITECTURE bdf_type OF tau2_temp_calculate IS

COMPONENT temp_table

port (

onchip_memory2_0_clk1_clk : in std_logic;

onchip_memory2_0_clk2_clk : in std_logic;

onchip_memory2_0_reset1_reset : in std_logic;

onchip_memory2_0_reset2_reset : in std_logic;

onchip_memory2_0_s1_address : in std_logic_vector(13 downto 0);

onchip_memory2_0_s1_clken : in std_logic;

onchip_memory2_0_s1_chipselect : in std_logic;

onchip_memory2_0_s1_write : in std_logic;

onchip_memory2_0_s1_readdata : out std_logic_vector(31 downto 0);

onchip_memory2_0_s1_writedata : in std_logic_vector(31 downto 0);

onchip_memory2_0_s1_byteenable : in std_logic_vector(3 downto 0);

onchip_memory2_0_s2_address : in std_logic_vector(13 downto 0);

onchip_memory2_0_s2_chipselect : in std_logic;

onchip_memory2_0_s2_clken : in std_logic;

onchip_memory2_0_s2_write : in std_logic;

onchip_memory2_0_s2_readdata : out std_logic_vector(31 downto 0);

onchip_memory2_0_s2_writedata : in std_logic_vector(31 downto 0);

onchip_memory2_0_s2_byteenable : in std_logic_vector(3 downto 0)

);

END COMPONENT;

begin

temp_table_inst: temp_table

PORT MAP(

onchip_memory2_0_s1_readdata=> onchip_memory2_0_s1_readdata,

onchip_memory2_0_s1_address => onchip_memory2_0_s1_address,

onchip_memory2_0_clk1_clk=>onchip_memory2_0_clk1_clk,

onchip_memory2_0_reset1_reset=>onchip_memory2_0_reset1_reset,

onchip_memory2_0_s1_clken => onchip_memory2_0_s1_clken,

onchip_memory2_0_s1_chipselect=> onchip_memory2_0_s1_chipselect,

onchip_memory2_0_s1_write => onchip_memory2_0_s1_write,

onchip_memory2_0_s1_writedata=> onchip_memory2_0_s1_writedata,

onchip_memory2_0_s1_byteenable=> onchip_memory2_0_s1_byteenable,

onchip_memory2_0_clk2_clk =>onchip_memory2_0_clk2_clk,

onchip_memory2_0_reset2_reset => onchip_memory2_0_reset2_reset,

onchip_memory2_0_s2_address => onchip_memory2_0_s2_address,

onchip_memory2_0_s2_chipselect => onchip_memory2_0_s2_chipselect,

onchip_memory2_0_s2_clken => onchip_memory2_0_s2_clken,

onchip_memory2_0_s2_write => onchip_memory2_0_s2_write,

onchip_memory2_0_s2_readdata =>onchip_memory2_0_s2_readdata,

onchip_memory2_0_s2_writedata => onchip_memory2_0_s2_writedata,

onchip_memory2_0_s2_byteenable => onchip_memory2_0_s2_byteenable

);

END bdf_type;