Dual Configuration IP does not trigger reconfiguration in MAX 10

Hi,

When using the Dual Boot IP, you should enable the CONFIG_SEL pin options to determine which image the MAX 10 need to be boot up. Then use the config_sel_overwrite bit and config_sel bit to switch between the image 0 and 1 without power cycle.

Did you program the MAX10 with image 0 and image 1 from the beginning then whenever there is a failure in one of the image it should revert to the other image? How do you identify the difference between image 0 and image 1 in the first place? I suggest that you should have 2 different images showing different function for as image 0 and image 1 respectively. This would help to show different image being load into the MAX 10 when power up by CONFIG_SEL pin and by the Dual Boot IP.

1. Program the MAX 10 CFM0 and CFM1/2 with the .pof (2 different .sof file to help showing different image) via the Quartus programmer.

2. Then test the CONFIG_SEL pin to boot the MAX 10 with image 0 and image 1. This will show you the correct expected behavior.

3. Then using the Dual Boot IP, set the config_sel_overwrite bit and config_sel to switch image 0 and image 1.

a. In offset 1, write Bit 0 — set value 1 to this register config_sel_overwrite

b. In offset 1, write Bit 1— writes config_sel either with value 0 or 1 to load from configuration image 0 or 1 respectively.

c. In offset 0, write Bit 0 — set value 1 to trigger reconfiguration.

Regards,

Nooraini

Nooraini, thank you for some help.

I enabled dual compressed images. The design has a way to ask the question, what revision are you? And I created two sof images, with two different revisions. Then I combine the two sof files into a pof and program the device by JTAG.

Both images enable all the pins DEV_CLRn, DEV_OE, nCONFIG, nSTATUS, CONF_DONE, and CONFIG_SEL. I have control over these pins via another path in the design outside the FPGA. I can change images using the external pins without any problem, demonstrating the images are good, and that I can see the two different revisions after reconfiguration.

Then I used the IP to try to duplicate reconfiguration. First I used config_sel_overwrite and config_sel, and the nCONFIG pin (external). I have demonstrated that these bits work, because I can change images, and I can change the CONFIG_SEL pin and it is ignored.

Then finally I try to trigger reconfiguration with the IP using offset 0 bit 0 equals 1, and this does not work. So to debug, I created a soft with Signal Tap setup, and load to SRAM. When the bit is set to one, I see alt_dual_boot|ru_rcofig toggle high. This demonstrates that the IP is receiving the offset zero command and issuing the signal.

No doubt there is more logic between this signal and the IP, and it is mixed with the nCONFIG pin, perhaps with an OR gate somewhere. What I don't know is if there is some other setting that must be used to enable ru_config to work, or some limitation on this particular version of the MAX 10, or some external state that effects it, etc. I get the same results on two pieces of hardware. I am using Quartus 17.

I'll add to this that I put a scope on STATUS/ and CONF-DONE, and when CONFIG/ is asserted at the pin, I see them go low and high, and when offset 0 bit one is used, these pins do not change state. I did this to ensure there was not a reconfiguration/load of the image combined with a failure. I internal method just fails to trigger.

Adding my settings...

set_global_assignment -name FAMILY "MAX 10"

set_global_assignment -name DEVICE 10M16SAU169I7G

set_global_assignment -name TOP_LEVEL_ENTITY i2cspy

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.1

set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:40:09 JUNE 26, 2014"

set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

#============================================================

# Design Pin Assignments

#============================================================

...

#============================================================

# General configuration

#============================================================

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON

set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON

set_global_assignment -name UNIPHY_TEMP_VER_CODE 2093439050

set_global_assignment -name ECO_REGENERATE_REPORT ON

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON

set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"

set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

set_global_assignment -name ENABLE_SIGNALTAP ON

set_global_assignment -name USE_SIGNALTAP_FILE i2scope.stp

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON

set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON

set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM

set_global_assignment -name QII_AUTO_PACKED_REGISTERS "MINIMIZE AREA"

set_global_assignment -name MUX_RESTRUCTURE OFF

set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON

set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON

set_global_assignment -name SMART_RECOMPILE OFF

set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name ENABLE_OCT_DONE OFF

set_global_assignment -name USE_CONFIGURATION_DEVICE OFF

set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "DUAL IMAGES"

set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise

set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall

set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON

set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "100 %"

set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 169

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7

set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005

set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF

set_global_assignment -name POWER_USE_PVA OFF

set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE "100 %"

set_global_assignment -name ENABLE_BOOT_SEL_PIN ON

set_global_assignment -name ENABLE_CONFIGURATION_PINS ON

set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON

set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON

set_global_assignment -name AUTO_RESTART_CONFIGURATION ON

set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"

set_global_assignment -name STATE_MACHINE_PROCESSING AUTO

set_global_assignment -name SAFE_STATE_MACHINE OFF

set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES ON

set_global_assignment -name PARALLEL_SYNTHESIS ON

set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON

set_global_assignment -name REMOVE_DUPLICATE_REGISTERS ON

set_global_assignment -name AUTO_CARRY_CHAINS ON

set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION ON

set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON

set_global_assignment -name AUTO_RESOURCE_SHARING OFF

set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING ON

set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION ON

set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT OFF

set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF

set_global_assignment -name SYNTH_MESSAGE_LEVEL MEDIUM

set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES AUTO

Adding the registers removed during synthesis, in case anyone knows the internal design and can detect a problem.

Hi MJone6,

Why do you need to control the nCONFIG pin? There is no need to control the nCONFIG pin at all. You only need to set these 2 bit config_sel_overwrite bit and config_sel bit before triggering the reconfiguration. Did you try to read Read reconfiguration trigger status to check the actual error? Previously I have tested the Dual Boot IP functionin correctly with a simple code as shown in the snippet below:

	case 2:	/*set CONFIG_SEL overwrite to 1 and CONFIG_SEL to 0*/
			 IOWR(DUAL_BOOT_0_BASE, 1, 0x00000001);
			state++;
	break;
 
	case 3: /*Trigger reconfiguration to Image 0*/
			if(IORD(DUAL_BOOT_0_BASE,3) == 0)
			{
			IOWR(DUAL_BOOT_0_BASE, 0, 0x00000001);
			state=0;
			}
	 break;
 
	case 4: /*set CONFIG_SEL overwrite to 1 and CONFIG_SEL to 1*/
		   IOWR(DUAL_BOOT_0_BASE, 1, 0x00000003);
		  state++;
         break;
 
   case 5: /*Trigger reconfiguration to Image 1*/
	       if(IORD(DUAL_BOOT_0_BASE,3) == 0)
	     {
	     IOWR(DUAL_BOOT_0_BASE, 0, 0x00000001);
	    state=0;
	      }
	 break;

Regards,

Nooraini

Hi MJone6,

Did you try to read Read reconfiguration trigger status to check the actual error? I have migrated the existing AN741 example design from the v16.1.0 design store (in the link below) into Quartus Prime v18.0 today and tested successfully.

https://fpgacloud.intel.com/devstore/platform/16.1.0/Standard/max10-remote-system-upgrade-rsu-over-uart-for-nios-ii-processor/

You can refer to the attached .zip file which contain the designs. Both the .qar designs has simple LEDs design to indicate different image between factory image (CFM0) and application1 image (CFM1/2). There is no issue with the Dual Boot IP that I have tested today. You can use the example design to compare with yours if there are any difference settings.

Regards,

Nooraini