Nooraini_Y_Intel
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Re: FPGA development kit problem
Hi lzhou5, Thank you for the correct invoice information. The internal team has validated the Arria 10 dev kit as under warranty. Please contact your local authorized Intel Distributors to process with the RMA process. Thank you Regards, Nooraini2.5KViews0likes0CommentsRe: PAC Arria 10 GX, reconfiguration not working on 1.2PV
Hi, Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you. Regards, Nooraini1.8KViews0likes0CommentsRe: lspci while running DMA traffic crashes linux server
Hi, Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you. Regards, Nooraini998Views0likes0CommentsRe: We need to keep the overall latency from FPGA request to memory device and back to FPGA at a minimum. We have come across a situation that a 1SG280HU2F50E2VGS1 device works and a 1SM21BHU2F53E2VGS1 device does not.
Hi, Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you. Regards, Nooraini760Views0likes0CommentsRe: "CONF_DONE pin failed to go high in device 1" - Arria 10 FPGA Dev Kit
Hi Karl, Apologize for the delay, I missed this update. Base on all the testing findings and result, even with the default settings the Arria 10 device is not able to configure, most probably the CONF_DONE pin is no longer functioning as expected. Regards, Nooraini5.4KViews0likes0CommentsRe: Can you use the non-volatile key from the FPGA (Cyclone V) in a design?
Hi TMayd, Yes, the programmed non-volatile key is use to decrypt the configuration bitstream during the configuration process. The general process flow is shown in figure 1 from AN556. Once you program the non-volatile key, is it OTP, there is no way to repogram with a different value. You can generate multiple key files and encrypted image files . However once you program the non-volatile key into Cyclone V, the decryption engine can only decrypt the matching encrypted image. Regards, Nooraini2KViews0likes0CommentsRe: Can you use the non-volatile key from the FPGA (Cyclone V) in a design?
Hi TMayd, Yes, you can program a non-volatile key into the Cyclone V device. However the programmed key information cannot be read out since it is program into the polyfuse and not a register. For detials, you can refer to AN556:Using the Design Security Features in Intel® FPGAs document in the following link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an556.pdf Regards, Nooraini2KViews0likes1CommentRe: remote update IP with cyclone10 LP
Hi NZami, What is the reconfiguration trigger condition value that you have read back during factory image? Since the FPGA gets revert back into the factory image then you should be able to read back the reconfiguration trigger condition value. You need to set the param[] = 111, read_source[]=01 and trigger the read_param signal. Then when the busy signal is low monitor the data_out[] for the reconfiguration trigger condition value. You can use Signal Tap to monitor these signals. How did you write the .rpf file into the flash device? The default generated .rpd file from Quartus tools is little endian format. By default the programming the .jic/pof file, the Quartus programmer will perform the bit swapping (LSb first) before writing the data into the EPCS/EPCQ/EPCQA device. Thus you need to perform the bit swapping when using the little endian .rpd file before writing the data into EPCS/EPCQ/ECPQA device. If you set the big endian option in the Convert Programming tools when generation the .rpd file, then you don’t require to perform the bit swapping since the generated .rpd file is in big endian format. Regards, Nooraini2.6KViews0likes0CommentsRe: Intel FPGA University Program Donation Request Ticket [BR11964] for PSG.university@intel.com related.
Hi G.Senthil Kumar, Currently I'm checking with the internal team on this request since we do not handle such Intel FPGA University Program Donation Request here in the forum. Please do expect delay as we need time to check with the correct team. Thank you. Regards, Nooraini1.4KViews0likes0Comments