I do NOT want to control nCONFIG, it is the only thing that works. My FPGA Verilog basically does this:
if(IORD(DUAL_BOOT_0_BASE,3) == 0)
{
IOWR(DUAL_BOOT_0_BASE, 0, 0x00000001);
state=0;
}
And it DOES NOT WORK. The status returned from offset 3 is ZERO. Yet it DOES NOT WORK.
The fundamental problem is I am doing exactly the same thing you do, but it does not work. So the question is what else matters?
Everything else in my discussion about what I did is an attempt to find out what else matters that is not obvious. So I did lots of experiments, like disable nCONFIG, used Signal Tap to trace the signals down to ru_... and see it actuate and it looks good. So I am ASSUMING, there is some SETTING in the project that matters. So I even looked at all the settings in the Nios project for clues and everything was how I set my project. It could even be some crazy synthesis error, device bug, not supported and not documented that my 10M16 does not support it, etc.
I know it is hard to believe I am not doing just what you are showing, but I am, because I can see the signal assert in the IP to reconfigure and I can see the status is ZERO with Signal Tap as well. Also, I have proven that the config_sel_overwrite and config_sel work. It is just that reconfigure bit does nothing. And there is no visibility into how the Hard IP is designed and other logic it might be connected to, so it requires an Intel person to look into that for other dependencies that are not well documented.
Mike
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