Dual Configuration IP does not trigger reconfiguration in MAX 10

Nooraini, thank you for some help.

I enabled dual compressed images. The design has a way to ask the question, what revision are you? And I created two sof images, with two different revisions. Then I combine the two sof files into a pof and program the device by JTAG.

Both images enable all the pins DEV_CLRn, DEV_OE, nCONFIG, nSTATUS, CONF_DONE, and CONFIG_SEL. I have control over these pins via another path in the design outside the FPGA. I can change images using the external pins without any problem, demonstrating the images are good, and that I can see the two different revisions after reconfiguration.

Then I used the IP to try to duplicate reconfiguration. First I used config_sel_overwrite and config_sel, and the nCONFIG pin (external). I have demonstrated that these bits work, because I can change images, and I can change the CONFIG_SEL pin and it is ignored.

Then finally I try to trigger reconfiguration with the IP using offset 0 bit 0 equals 1, and this does not work. So to debug, I created a soft with Signal Tap setup, and load to SRAM. When the bit is set to one, I see alt_dual_boot|ru_rcofig toggle high. This demonstrates that the IP is receiving the offset zero command and issuing the signal.

No doubt there is more logic between this signal and the IP, and it is mixed with the nCONFIG pin, perhaps with an OR gate somewhere. What I don't know is if there is some other setting that must be used to enable ru_config to work, or some limitation on this particular version of the MAX 10, or some external state that effects it, etc. I get the same results on two pieces of hardware. I am using Quartus 17.