Hello guys, Does intel offer an FPGA that supports DP RX and MIPI DSI TX? If yes, does the FPGA have a D-PHY bank or is it implementing D-PHY through external resistors? Lastly, are there any reference designs for that FPGA to bridge DP over to MIPI DSI? Regards, Pascal.

Hi Pascal,Sorry for the confusion.Byright the * should has a clearer note mentioned something like below IP solution offered may vary on different FPGA product family. Pls check IP solution user guide doc for detail Regards,dlim

Hi Pascal,Sure, I can answer few more questions for you. just FYI... Intel support structure is on a case by case basic. That's why we always encourage customer to file new case for new enquiry.Anyway, now to your questionsI am not familiar with MIPI implementation as I explained to you earlier it's not direct support from Intel. Are you referring to IO pin count or transceiver pin count here ? Cyclone V FPGA is offer in many different package with different pin count support. You can checkout more from below Cyclone V ordering code dochttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51001.pdfFor the resource utilization on DP MST (2 channel)I would say the resource consumption should be between SST and MST (4 channel) but you will need to compile the DP IP in Quartus to checkout the detailThanks.Regards,dlim

HI,Unfortunately Intel doesn't has DP to MIPI conversion IP. Both IP is sold as individual standalone IP only.For DP IP :Intel does offer DP IP solution. You can checkout below DP user guide for more infohttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf For MIPI IP :Intel doesn't offer MIPI IP solution in house. We are relying on 3rd party design house to offer MIPI IP hence I am not sure about the design implementation detailI found out 2 design house that provide MIPI solution. Feel free to engage with themhttps://www.mikroprojekt.hr/products/system-solution/mipi-cameras-displays/mipi-dsi-solutionhttps://www.rambus.com/interface-ip/controllers/mipi-controllers/Thanks.Regards,dlim

Hello Deshi, Thanks for the reply. I see that the MAX 10 FPGA is not included in the supported devices for the DP IP. Is there anyway to make the DP IP work on the MAX 10 FPGA? Regards, Pascal.

Hi Pascal,Max10 PLD is targeting low-cost market that doesn't support transceiver channel which is required by Intel DP IP. This explained why you won't see Intel DP IP offered in Max 10.You can consider to upgrade to higher grade FPGA like Cyclone V or Arria V for even Cyclone 10 GX for Intel DP IP support.Thanks.Regards,dlim

DP to MIPI | Altera Community

11 Replies

Deshi_Intel
Regular Contributor
5 years ago
Hi Pascal,

Sorry for the confusion.

Byright the * should has a clearer note mentioned something like below
IP solution offered may vary on different FPGA product family. Pls check IP solution user guide doc for detail

Regards,
dlim
- PascalPolygon
  New Contributor
  5 years ago
  Hello @Deshi_Intel
  
  Thank you, I think we are going to go with the Cyclone V. Thanks for the helpful information.
  
  Regards,
  
  Pascal.
Deshi_Intel
Regular Contributor
5 years ago
Hi Pascal,

Sure, I can answer few more questions for you.

just FYI... Intel support structure is on a case by case basic. That's why we always encourage customer to file new case for new enquiry.

Anyway, now to your questions

I am not familiar with MIPI implementation as I explained to you earlier it's not direct support from Intel. Are you referring to IO pin count or transceiver pin count here ?
Cyclone V FPGA is offer in many different package with different pin count support. You can checkout more from below Cyclone V ordering code doc
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51001.pdf
For the resource utilization on DP MST (2 channel)
I would say the resource consumption should be between SST and MST (4 channel) but you will need to compile the DP IP in Quartus to checkout the detail

Thanks.

Regards,
dlim
- PascalPolygon
  New Contributor
  5 years ago
  @Deshi_Intel ,
  
  Thanks for the reply, I have more questions about the cyclone V and MIPI. I'll post a new question about those.
  
  Regards,
  
  Pascal.
Deshi_Intel
Regular Contributor
5 years ago
HI,

Unfortunately Intel doesn't has DP to MIPI conversion IP. Both IP is sold as individual standalone IP only.

For DP IP :
Intel does offer DP IP solution. You can checkout below DP user guide for more info
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf

For MIPI IP :
Intel doesn't offer MIPI IP solution in house. We are relying on 3rd party design house to offer MIPI IP hence I am not sure about the design implementation detail
I found out 2 design house that provide MIPI solution. Feel free to engage with them
https://www.mikroprojekt.hr/products/system-solution/mipi-cameras-displays/mipi-dsi-solution
https://www.rambus.com/interface-ip/controllers/mipi-controllers/

Thanks.

Regards,
dlim
- PascalPolygon
  New Contributor
  5 years ago
  Hello Deshi,
  
  Thanks for the reply. I see that the MAX 10 FPGA is not included in the supported devices for the DP IP. Is there anyway to make the DP IP work on the MAX 10 FPGA?
  
  Regards,
  
  Pascal.
Deshi_Intel
Regular Contributor
5 years ago
Hi Pascal,

Max10 PLD is targeting low-cost market that doesn't support transceiver channel which is required by Intel DP IP.

This explained why you won't see Intel DP IP offered in Max 10.

You can consider to upgrade to higher grade FPGA like Cyclone V or Arria V for even Cyclone 10 GX for Intel DP IP support.

Thanks.

Regards,
dlim
- PascalPolygon
  New Contributor
  5 years ago
  Hello Deshi,
  
  Thank you. Here is where my confusion is coming from. On this page (https://www.intel.com/content/www/us/en/products/programmable/fpga/max-10/features.html) DisplayPort appears as a video interface for the MAX 10 FPGA, but there is an asterisk. What does that mean?
  
  Regards,
  
  Pascal.
Deshi_Intel
Regular Contributor
5 years ago
Hi Pascal,

You are welcome !

Alright, I am setting this case to closure.

Feel free to file new forum post if you still have enquiry in future.

Thanks.

Regards,
dlim
- PascalPolygon
  New Contributor
  5 years ago
  @Deshi_Intel ,
  
  Before you close it, one more question. Does the Cyclone V have enough I/O's to drive 2 4-lane DSI channels. That is, I would like to drive 2 mipi displays not just one (8 data lanes, 2 clock lanes).
  
  Regards,
  
  Pascal.
  - PascalPolygon
    New Contributor
    5 years ago
    @Deshi_Intel
    
    Furthermore, based on this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf
    
    The difference in resource utilization between SST, and MST(4 streams) is pretty significant. I would like to do MST (2 streams), would that be the same resource utilization as 4 streams or half of it?
    
    Regards,
    
    Pascal.

Forum Discussion

DP to MIPI

11 Replies

Recent Discussions

FPGA issue on electronic board

MAX10 RSU upgrade succeeds, but device boots Factory image instead of Application

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger

Max10 FPGA Programming with .pof file

About ALTIOBUF simulation