Forum Discussion
PascalPolygon
New Contributor
New ContributorDP to MIPI
Hello guys,
Does intel offer an FPGA that supports DP RX and MIPI DSI TX?
If yes, does the FPGA have a D-PHY bank or is it implementing D-PHY through external resistors?
Lastly, are there any ...
Deshi_Intel
Regular Contributor
Regular ContributorHi Pascal,
You are welcome !
Alright, I am setting this case to closure.
Feel free to file new forum post if you still have enquiry in future.
Thanks.
Regards,
dlim
PascalPolygonNew Contributor
New ContributorBefore you close it, one more question. Does the Cyclone V have enough I/O's to drive 2 4-lane DSI channels. That is, I would like to drive 2 mipi displays not just one (8 data lanes, 2 clock lanes).
Regards,
Pascal.
- PascalPolygon
Furthermore, based on this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf
The difference in resource utilization between SST, and MST(4 streams) is pretty significant. I would like to do MST (2 streams), would that be the same resource utilization as 4 streams or half of it?
Regards,
Pascal.
