Deshi_Intel
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Re: Sending/Receiving Data to/from Altera DE2-115 via Ethernet
Hi, The first thing you need to take note is Intel FPGA triple speed ethernet (TSE) IP solution doesn't cover the whole Ethernet OSI layer and only reach until MAC layer. Meaning user is expected to build your top level application software to interact with TSE IP in the FPGA Most likely you won't find direct fit reference design that can match with DE2-115 board directly but below is some link that you can explore to find something closer to your design requirement Checkout DE2-115 board website directly to search for reference design https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=2 In general, you can find most of FPGA reference design in below link. For instance, you can search using "simple socket" keyword https://fpgacloud.intel.com/devstore/?search=simple%20socket Thanks. Regards, dlim1KViews0likes0CommentsRe: 100G core missing SOP/EOP handling on TX
Hi, I would expect the Tx MAC IP to wait for the completion of either missing SOP or EOP then assert l8_txstatus_error[6:0]. However, this issue shouldn't happen in the first place and should be taken care by the HOST application. If worst case there is issue with transmitted packet then I expect the HOST application to assert "l8_tx_error" to alert TX MAC IP Feel free to play around and test it out in simulation design Thanks. Regards, dlim728Views0likes0CommentsRe: some questons about agilex
Hi, Agilex I-series CXL interface is a hard IP. For new product feature, availability and pricing related enquiry, kindly reach out and consult your region local Intel sales or Intel distributor team. They can better assist you on your enquiry This Intel forum community is not the right place for such enquiry. Thanks for your understanding Regards, dlim759Views0likes0CommentsRe: deinterlace IP
Sorry, typo in my earlier post When bus width goes higher, the expected operating frequency should goes lower. Assuming bus width = 128, required operating frequency = xxx MHz when bus width = 256, required operating frequency = xxx MHz divided by 2 when bus width = 512, required operating frequency = xxx MHz divided by 42.8KViews0likes0CommentsRe: deinterlace IP
Hi, I am not sure I am following your explanation here. Sorry, this is English forum so I am having tough time to understand chinese translation here When bus width goes higher, the expected operating frequency should goes lower. Assuming bus width = 128, required operating frequency = 1x when bus width = 256, required operating frequency = 1x divide by 2 when bus width = 256, required operating frequency = 1x divide by 4 Thanks. Regards, dlim2.8KViews0likes0CommentsRe: About PRESERVE_UNUSED_XCVR_CHANNELfor transceiver application
Hi Lambert, Quartus continue to enhance on its fitting algorithm and feature from version to version but I am not the right support agent to advise you on Quartus feature. You can file new forum post mention about your latest finding then Intel will be able to assign Intel FPGA software team support agent to better advise you on the Quartus feature support and changes. Do take note in your new forum post, pls ensure you type in the right keyword mention about the fitting algorithm difference between Quartus version so that you forum thread can be routed to the right Intel software support agent to help you up Thanks. Regards, dlim2.9KViews0likes1CommentRe: Cyclone 10 HDMI fitter error
HI, So your intention is to use SDI IP and not HDMI IP ? Sorry but I am not familiar with SDI IP implementation, hence can't give you further advise. But from the look of this issue, likely this is limitation of NativePHY IP itself where the XCVR_CONFIG_GROUP command can only works with same logical channel as I explained to you earlier. I am not aware of any workaround. so you must either use same logical channel to fit into same physical channel pair or totally split Tx and Rx channel into different physical channel then there is no need to merge them anymore Thanks. Regards, dlim1.3KViews0likes0CommentsRe: Cyclone 10 HDMI fitter error
HI, the fitter error was due to invalid "XCVR_RECONFIG_GROUP" setting implementation. Your design qsf is forcing Tx3 channel and Rx2 channel into same XCVR_RECONFIG_GROUP end up into fitter error Only same logical transceiver channel pair can be group together. For instance, Tx2 + Rx2 or Tx1 + Rx1 and etc I modified your design qsf to move Rx2 to pair with Tx2 then fitter compilation is successful Thanks. Regards, dlim1.3KViews0likes1Comment