DP to MIPI

Hi Pascal,

Sure, I can answer few more questions for you.

just FYI... Intel support structure is on a case by case basic. That's why we always encourage customer to file new case for new enquiry.

Anyway, now to your questions

1. I am not familiar with MIPI implementation as I explained to you earlier it's not direct support from Intel. Are you referring to IO pin count or transceiver pin count here ?

• Cyclone V FPGA is offer in many different package with different pin count support. You can checkout more from below Cyclone V ordering code doc
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51001.pdf
• For the resource utilization on DP MST (2 channel)
  • I would say the resource consumption should be between SST and MST (4 channel) but you will need to compile the DP IP in Quartus to checkout the detail

Thanks.

Regards,

dlim