Downloading Error when both 3V I/O & tranceivers are used in a project

Hi,

Thanks for your answer!

I update Quartus to the lates 21.1, but it doesn't work, the appearance is same.

Btw, my device is Stratix 10(1SX280 series).

So, is there any other possible solutions? Thank you !

Hi,

Thank you for reply!

I'm using USB-blaster, not USB-blaster II.

I replace the OSC from 24MHz to 6MHz in the USB-blaster, the TCK frequency slowed, but my problem is still there.

Only one device in this downloading chain.

Expecting for your reply!

Hi:

Yes, the refclk is running. I make a mini-system design to download, it works.

This design only include three IPs(release_reset, clock, PLL), and some very simple logics(a counter connecting to a GPIO to drive a LED, to make a breathing lamp). This design can be downloaded and worked correctly.

I also make a design with instantiation of xcvr & 3V I/O seperately, with the same constrains of PCIe mentioned above, this design can also be downloaded, so it looks like only when the tranceiver & 3V I/O have internal relationshaips with each other, can trigger this problem.

Hi,

I checked the global refclk is working correctly(25MHz), otherwise, the mini-system won't work.

In my design, PCIe module is uesed as EP(end point), and working clk is provided by the Host(root complex, in my system it's PC). This clk is assigned to the dedicated pin for PCIe Hard IP, but it's floated(not connected) when downloading. So, does it matter?

Two more clks(both are 156.25MHz) connect to the tranceiver, but not used for PCIe, designed to use for other two high-speed transmition.

One is connected to the same group of tranceivers with PCIe, but not the same bank(PCIe used bank 1K,1L, 156.25MHz used for 1N,1M), the other clk connected to the other group of tranceivers.

Hi,

My problem solved!!

The key reason is the PCIe refclk not connected when dowloading. After cables connected between RC & EP, the program could be downloaded correctly. But when I used Cyclone V in my previous project, it's no need to connect cables between RC & EP when downloading program to FPGA, btw, it's Gen 1 of PCIe at that time, so is it new feature for S10 devices or Gen3 of PCIe?

Two more questions :

1. It looks like the refclk of RC must be stable when downloading the program of EP, what's the timing requirements, eg. how long should the refclk be stable after PoR?

2. In AS x4 booting mode, I drive low the "nConfig" pin to reboot the FPGA, after 3 times, it crashed, no data transfer between FPGA & flash. is that correct? or my usage is wrong?