New Contributor
Regular ContributorHi,
Could you use the SDM Toolkit to check the configuration status after the JTAG configuration failure? You may follow the guide in Chapter 7.4.1 of https://www.intel.com/content/www/us/en/programmable/documentation/sss1439972793861.html.
New ContributorHi,
My problem solved!!
The key reason is the PCIe refclk not connected when dowloading. After cables connected between RC & EP, the program could be downloaded correctly. But when I used Cyclone V in my previous project, it's no need to connect cables between RC & EP when downloading program to FPGA, btw, it's Gen 1 of PCIe at that time, so is it new feature for S10 devices or Gen3 of PCIe?
Two more questions :
1. It looks like the refclk of RC must be stable when downloading the program of EP, what's the timing requirements, eg. how long should the refclk be stable after PoR?
2. In AS x4 booting mode, I drive low the "nConfig" pin to reboot the FPGA, after 3 times, it crashed, no data transfer between FPGA & flash. is that correct? or my usage is wrong?
