Altera_Forum
Honored Contributor
Honored Contributordoubt regarding RAM
how do i save 64 bits onto a RAM at a time and take out 16bits output at a time?:confused:
Forum Discussion
9 Replies
Altera_ForumMake use of byteenable signals of Avalon-MM interface if you are designing any component
- Altera_Forum
What kind of RAM your targetting at? Internal or external? Internal RAM can simply use two ports of different width.
- Altera_Forum
my design is not targeting any specific device... it would be helpful if there was a general solution for such a problem across FPGA vendors...
- Altera_Forum
The Altera solution is the MegaFunction called LPM_RAM_DP, it is a dual port RAM module in which you can set different widths for the input and output ports.
And of course you may write it in VHDL or Verilog so it becomes a cross-vendor portable design. - Altera_Forum
My question also wasn't related to a specific device. It was regarding the intended mode of operation.my design is not targeting any specific device
If we are discussing internal RAM, it can be be generally inferred from HDL code. But the mapping of dual-port RAM with different port widths can't defined from HDL, to my opinion, it must be regarded implementation dependant. At this point low-level vendor libraries can't be avoided, portability can hardly be achieved.And of course you may write it in VHDL or Verilog so it becomes a cross-vendor portable design - Altera_Forum
sorry FVM,
i was responding to the Avalon idea..... anyway, when you say internal memory, do you mean to say the memory synthesized from Logic elements or the on chip memory in a FPGA? - Altera_Forum
I meant on-chip RAM. Register based memory can be accessed arbitrarily without any restrictions anyway (apart from avoiding multiple sources for writing). On chip RAM, that is available dual ported with most FPGA families is perfectly suited to implement buffer memories connecting different design partitions, possibly with different clock domains.
I have e. g. a parameter strorage in internal RAM. It is written or read from a uP through a 16-Bit data bus and accesses as a 128-Bit parameter block internally. - Altera_Forum
i tried something like this and got a register based RAM implemented.. can anyone suggest any modifications so that a on-chip internal RAM is inferred?
entity ram_16_128 isport ( ip_clk :in std_logic;
ip_write_en :in std_logic;
op_ram_addr :in std_logic_vector (1 downto 0);
ip_data_in :in std_logic_vector (63 downto 0);
op_data_out :out std_logic_vector (15 downto 0));
end ram_16_128;
architecture arch_ram_16_128 of ram_16_128 is
type ram_type is array(3 downto 0) of std_logic_vector (15 downto 0);
signal ram : ram_type;
signal s_ram_addr : std_logic_vector(2 downto 0);
begin
process (ip_clk)
begin
if (ip_clk'event and ip_clk = '1') then
if (ip_write_en = '1') then
ram(0) <= ip_data_in(63 downto 48);
ram(1) <= ip_data_in(47 downto 32);
ram(2) <= ip_data_in(31 downto 16);
ram(3) <= ip_data_in(15 downto 0);
end if;
s_ram_addr <= op_ram_addr;
end if;
end process;
op_data_out <= ram(conv_integer(op_ram_addr));
end arch_ram_16_128;
- Altera_Forum
It's basically an example why the mapping of dual-port ram with different port widths can't be defined from hdl as i mentioned. Cause you cant define a mapping of four 16-Bit RAM words to a single 64-Bit word at the seconde port, you are trying to write four RAM words in one clock cycle. That can't work, you can only write one address at each clock cycle!
The only solution is to use a low-level vendor library, that means a RAM MegaFunction when using Altera FPGA. P.S.: This doesn't necessarily imply using the MegaWizard, you can also directly instantiate altsyncram in your HDL code, if you learned the parameters.
