doubt regarding RAM

my design is not targeting any specific device

My question also wasn't related to a specific device. It was regarding the intended mode of operation.

And of course you may write it in VHDL or Verilog so it becomes a cross-vendor portable design

If we are discussing internal RAM, it can be be generally inferred from HDL code. But the mapping of dual-port RAM with different port widths can't defined from HDL, to my opinion, it must be regarded implementation dependant. At this point low-level vendor libraries can't be avoided, portability can hardly be achieved.