doubt regarding RAM

It's basically an example why the mapping of dual-port ram with different port widths can't be defined from hdl as i mentioned. Cause you cant define a mapping of four 16-Bit RAM words to a single 64-Bit word at the seconde port, you are trying to write four RAM words in one clock cycle. That can't work, you can only write one address at each clock cycle!

The only solution is to use a low-level vendor library, that means a RAM MegaFunction when using Altera FPGA.

P.S.: This doesn't necessarily imply using the MegaWizard, you can also directly instantiate altsyncram in your HDL code, if you learned the parameters.