Forum Discussion
Altera_Forum
Honored Contributor
17 years agoi tried something like this and got a register based RAM implemented.. can anyone suggest any modifications so that a on-chip internal RAM is inferred?
entity ram_16_128 isport ( ip_clk :in std_logic;
ip_write_en :in std_logic;
op_ram_addr :in std_logic_vector (1 downto 0);
ip_data_in :in std_logic_vector (63 downto 0);
op_data_out :out std_logic_vector (15 downto 0));
end ram_16_128;
architecture arch_ram_16_128 of ram_16_128 is
type ram_type is array(3 downto 0) of std_logic_vector (15 downto 0);
signal ram : ram_type;
signal s_ram_addr : std_logic_vector(2 downto 0);
begin
process (ip_clk)
begin
if (ip_clk'event and ip_clk = '1') then
if (ip_write_en = '1') then
ram(0) <= ip_data_in(63 downto 48);
ram(1) <= ip_data_in(47 downto 32);
ram(2) <= ip_data_in(31 downto 16);
ram(3) <= ip_data_in(15 downto 0);
end if;
s_ram_addr <= op_ram_addr;
end if;
end process;
op_data_out <= ram(conv_integer(op_ram_addr));
end arch_ram_16_128;