doubt regarding RAM

I meant on-chip RAM. Register based memory can be accessed arbitrarily without any restrictions anyway (apart from avoiding multiple sources for writing). On chip RAM, that is available dual ported with most FPGA families is perfectly suited to implement buffer memories connecting different design partitions, possibly with different clock domains.

I have e. g. a parameter strorage in internal RAM. It is written or read from a uP through a 16-Bit data bus and accesses as a 128-Bit parameter block internally.