Device selection

Be sure to perform static timing analysis as well.

http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf

I don't think you'll have trouble meeting your 100 MHz for I/O timing.

Can't say about the internal logic, for that you really need to put a design together and run the timing analysis and/or gate level simulation.

Thanks for all your reply. We will most likely select the Cyclone IV device for this application. I believe good technical support is also a key factor in selection of devices, as I got no response from Lattice in both local sales and forum.

After I read the datasheet carefully, there is a section in I/O Timing, and it mentioned that there is an Excel-based I/O Timing worksheet. Then I download the worksheet and looked at the devices. The worse case delay is (tsu + tco), which equate to a little higher than 100MHz for a C8 speed grade. So I think it should be okay. We will install the software and further verify this with simulation.

BR - Henry

Most CPLDs have a different architecture than FPGAs.

MAX II CPLDs are the exception to the norm, as they are LE based, like a Cyclone FPGA. That said, they lack most (all?) of the other features found in FPGAs: memory blocks, dedicated multipliers, PLLs, etc, etc.

Back to timing:

Since the architecture is similar, the issues and tools are the same for MAX II and FPGAs.

Timing will depend greatly on your design. You need to implement the design and then see if it can meet your 100 MHz target.

Anyway, since you estimate you need 4K D-flip-flops, you need an FPGA. No CPLD has that many registers.

--- Quote Start ---

Hi GPK,

Thanks for your answer. But I think the CycloneIV is also using LUT for each LE (Logic Element). Then in terms of speed, that should be compatible with CPLD. I was told that there were uncertainty in FPGA timing for each compilation of the code, while the timing was certain for CPLD. That should be changed now with better software, etc.

--- Quote End ---

Hi,

as I said before the timing depends on your design. As long as the changes are small you will get nearly the same timing from compile to compile with Quartus.

Kind regards

GPK

Hi GPK,

Thanks for your answer. But I think the CycloneIV is also using LUT for each LE (Logic Element). Then in terms of speed, that should be compatible with CPLD. I was told that there were uncertainty in FPGA timing for each compilation of the code, while the timing was certain for CPLD. That should be changed now with better software, etc.

--- Quote Start ---

Hi GPK,

Okay, I have contacted local distributor to help me install the Quartus II software instead of downloading the software (8G total size) from the internet. I will try to play with this software and see if it can achieve my target.

Now let's go back to the discussion of CPLD versus FPGA. From what you said below: "the internal timings will not give you the answer your are looking for. The internal timings describe in my point of view only a theoretical speed, because the achievable clock speed depends more on your design. If you have e.g. a design with a lot of logical levels it will run very slow on every FPGA."

But I looked at the CycloneIV device and the architecture does not seem to be that much difference from that of the MAXII. It does seem that the CycloneIV can achieve the timing if I can have good control of the routing. So your statement "will run very slow" should apply to both CPLD and FPGA, not just FPGA. Correct?

It seems that CPLD is more target towards glue logic type of person, who is more concern on timing, while FPGA is more target towards high integration or ASIC replacement that is more concern on what IP they can stuff into one single device, so that is why FPGA manufacturer do not normally provide precise timing. But I think the FPGA manufacturers should provide some timing figures for typical implementation examples, to make it easier for device selection.

It seems for the same device cost, FPGA can do more than CPLD. So can I say that if I am willing to add an extra non volatile configuration device, FPGA is a better choice than CPLD?

--- Quote End ---

Hi,

the structure of an FPGA is diiferent compared to a CPLD. An FPGA is LUT-based, that means you don't find gates for your logic. All your logical functions will be programmed

in LUT's. Next difference are additional functions blocks like RAM, Multiplier etc... At least in Altera CPLD you will not find any of the functions. You see there are a lot of differences.

The decision what you should use depends on your requirements. If you only need a replacement for some glue logic use a CPLD, beause it will save board space and unit costs compared with an FPGA. If you need advancd functions like RAM, Multiplier etc.. you should choose a FPGA.

Kind regards

GPK

Hi GPK,

Okay, I have contacted local distributor to help me install the Quartus II software instead of downloading the software (8G total size) from the internet. I will try to play with this software and see if it can achieve my target.

Now let's go back to the discussion of CPLD versus FPGA. From what you said below: "the internal timings will not give you the answer your are looking for. The internal timings describe in my point of view only a theoretical speed, because the achievable clock speed depends more on your design. If you have e.g. a design with a lot of logical levels it will run very slow on every FPGA."

But I looked at the CycloneIV device and the architecture does not seem to be that much difference from that of the MAXII. It does seem that the CycloneIV can achieve the timing if I can have good control of the routing. So your statement "will run very slow" should apply to both CPLD and FPGA, not just FPGA. Correct?

It seems that CPLD is more target towards glue logic type of person, who is more concern on timing, while FPGA is more target towards high integration or ASIC replacement that is more concern on what IP they can stuff into one single device, so that is why FPGA manufacturer do not normally provide precise timing. But I think the FPGA manufacturers should provide some timing figures for typical implementation examples, to make it easier for device selection.

It seems for the same device cost, FPGA can do more than CPLD. So can I say that if I am willing to add an extra non volatile configuration device, FPGA is a better choice than CPLD?

--- Quote Start ---

Hi GPK,

I only have the block diagram drawn up in PPT. Is it okay to run a simulation?

Basically it is very simple, it has a 48 x 32 D-type flip flops, there are 48 data lines going into the flip flops inputs, and the flip flops are clocked serially to form a buffer that is 32 deep by 48 width. Once I receive a logic signal, it disable data loading and freeze the data inside these flip flops. Then the logic should load the D flip flops in each line into a shift register, so there should be 32 shift registers with a length of 48. Then I can slowly shift the data out from the shift registers to other IO pins.

So this is the most critical part which require as high a speed as possible. The target clock speed for this block is 100MHz. I am hoping the EP4CE6 can do the job. Thanks!

BR - Henry

--- Quote End ---

Hi Henry,

in Quartus you have a megawizard which offers some Ip blocks. Have a look to

http://www.altera.com/literature/ug/ug_shift_register_ram_based.pdf

Kind regards

GPK

Hi GPK,

I only have the block diagram drawn up in PPT. Is it okay to run a simulation?

Basically it is very simple, it has a 48 x 32 D-type flip flops, there are 48 data lines going into the flip flops inputs, and the flip flops are clocked serially to form a buffer that is 32 deep by 48 width. Once I receive a logic signal, it disable data loading and freeze the data inside these flip flops. Then the logic should load the D flip flops in each line into a shift register, so there should be 32 shift registers with a length of 48. Then I can slowly shift the data out from the shift registers to other IO pins.

So this is the most critical part which require as high a speed as possible. The target clock speed for this block is 100MHz. I am hoping the EP4CE6 can do the job. Thanks!

BR - Henry

--- Quote Start ---

Hi GPK,

Thanks for your reply. So it goes back to the situation between choosing FPGA or CPLD. Does it mean that if I choose a high gate count FPGA and keep its utilization to be small enough, then I might be able to meet the timing requirement? If so, is there a typical plot of utilization versus usable clock rate? Or, the only way to find this out is to install the software, design the schematic, and run the simulation, and finally find that the device cannot meet my requirement?

My circuit is actually very simple. It uses one single clock synchronize logic design, so what I need to know is the maximum achievable clock rate for the combinational logic plus the D flip flop delay (such as a synchronize 8-bit binary counter design), and it can be easily found out from most CPLD datasheet, but not for FPGA datasheet.

The MAXII could fit my needs, but unfortunately, its logic units cannot be converted into RAM bits to realize small FIFO or dual-port RAM. I could use D flip flops as RAM, but the MAXII does not have such large device to choose from. Other's CPLD such as those from Lattice or Actel have configurable RAM bits.

BR - Henry

--- Quote End ---

Hi Henry,

in case your design is ready I would run a P&R run with Quartus. It will give you all numbers you need.

Kind regards

GPK