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Hi GPK,
I only have the block diagram drawn up in PPT. Is it okay to run a simulation?
Basically it is very simple, it has a 48 x 32 D-type flip flops, there are 48 data lines going into the flip flops inputs, and the flip flops are clocked serially to form a buffer that is 32 deep by 48 width. Once I receive a logic signal, it disable data loading and freeze the data inside these flip flops. Then the logic should load the D flip flops in each line into a shift register, so there should be 32 shift registers with a length of 48. Then I can slowly shift the data out from the shift registers to other IO pins.
So this is the most critical part which require as high a speed as possible. The target clock speed for this block is 100MHz. I am hoping the EP4CE6 can do the job. Thanks!
BR - Henry
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Hi Henry,
in Quartus you have a megawizard which offers some Ip blocks. Have a look to
http://www.altera.com/literature/ug/ug_shift_register_ram_based.pdf Kind regards
GPK
Honored Contributor
