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Hello,
I am looking for a simple glue logic solution that has about 4k D-flip flops. The glue logic just involve simple counters, shift registers, and combination logic. But I need very tight timing data for the logic such as setup time, hold time, etc. I found that the MAXII datasheet has very detail timing data, but the Cyclone FPGA datasheet does not show any detail. All I can see from its handbook is that it can go up to a few hundred MHZ. But the MAXII might not have enough gates for my purpose. I do not want to install any software on my PC until I am sure I want to go for a particular device.
I look at other competitors web site and similar things happen. Most CPLD datasheet provides detail timing, but most FPGA datasheet is very vague on timing information.
BR - Henry
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Hi Henry,
the internal timings will not give you the answer your are looking for. The internal timings
describe in my point of view only a theoretical speed, because the achievable clock speed depends more on your design. If you have e.g. a design with a lot of logical levels it will run very slow on every FPGA.
Have a look to :
http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf In this document you will find at least some timings for the internal clock trees and a few other things.
Kind regards
GPK
Honored Contributor
