Device selection

Hi GPK,

Thanks for your reply. So it goes back to the situation between choosing FPGA or CPLD. Does it mean that if I choose a high gate count FPGA and keep its utilization to be small enough, then I might be able to meet the timing requirement? If so, is there a typical plot of utilization versus usable clock rate? Or, the only way to find this out is to install the software, design the schematic, and run the simulation, and finally find that the device cannot meet my requirement?

My circuit is actually very simple. It uses one single clock synchronize logic design, so what I need to know is the maximum achievable clock rate for the combinational logic plus the D flip flop delay (such as a synchronize 8-bit binary counter design), and it can be easily found out from most CPLD datasheet, but not for FPGA datasheet.

The MAXII could fit my needs, but unfortunately, its logic units cannot be converted into RAM bits to realize small FIFO or dual-port RAM. I could use D flip flops as RAM, but the MAXII does not have such large device to choose from. Other's CPLD such as those from Lattice or Actel have configurable RAM bits.

BR - Henry