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Hi GPK,
Thanks for your answer. But I think the CycloneIV is also using LUT for each LE (Logic Element). Then in terms of speed, that should be compatible with CPLD. I was told that there were uncertainty in FPGA timing for each compilation of the code, while the timing was certain for CPLD. That should be changed now with better software, etc.
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Hi,
as I said before the timing depends on your design. As long as the changes are small you will get nearly the same timing from compile to compile with Quartus.
Kind regards
GPK
Honored Contributor
