Device selection

Hi GPK,

Okay, I have contacted local distributor to help me install the Quartus II software instead of downloading the software (8G total size) from the internet. I will try to play with this software and see if it can achieve my target.

Now let's go back to the discussion of CPLD versus FPGA. From what you said below: "the internal timings will not give you the answer your are looking for. The internal timings describe in my point of view only a theoretical speed, because the achievable clock speed depends more on your design. If you have e.g. a design with a lot of logical levels it will run very slow on every FPGA."

But I looked at the CycloneIV device and the architecture does not seem to be that much difference from that of the MAXII. It does seem that the CycloneIV can achieve the timing if I can have good control of the routing. So your statement "will run very slow" should apply to both CPLD and FPGA, not just FPGA. Correct?

It seems that CPLD is more target towards glue logic type of person, who is more concern on timing, while FPGA is more target towards high integration or ASIC replacement that is more concern on what IP they can stuff into one single device, so that is why FPGA manufacturer do not normally provide precise timing. But I think the FPGA manufacturers should provide some timing figures for typical implementation examples, to make it easier for device selection.

It seems for the same device cost, FPGA can do more than CPLD. So can I say that if I am willing to add an extra non volatile configuration device, FPGA is a better choice than CPLD?