Device selection

Most CPLDs have a different architecture than FPGAs.

MAX II CPLDs are the exception to the norm, as they are LE based, like a Cyclone FPGA. That said, they lack most (all?) of the other features found in FPGAs: memory blocks, dedicated multipliers, PLLs, etc, etc.

Back to timing:

Since the architecture is similar, the issues and tools are the same for MAX II and FPGAs.

Timing will depend greatly on your design. You need to implement the design and then see if it can meet your 100 MHz target.

Anyway, since you estimate you need 4K D-flip-flops, you need an FPGA. No CPLD has that many registers.