Forum Discussion
Honored ContributorDelay chain design?
Hi
I am using the cycloneIII 3c120 kit to learn designing with FPGA. What I would like to do is a delay chain, in which a signal is delayed by each chain element on the order of 100..500ps. Since such small times can not be designed by clocked flip flops (?), I would like to use LEs, which produce delay just from entry to output. The amount of delay elements would be of the order of 20 to 100, since I would like to cover about 10 ns. Higher delays can be done synchronously. I think that such a delayline is not very precise, since the delay of each element might vary over time, temperature etc., but at least it could be causal in the sense that an earlier element should bring a smaller delay. Up to now, I have not been capable of making such a delay line. The elements exhibit very strange delays, even later elements bring smaller delays etc. I think, that this is a typical beginners question, any help is much appreciated best regards Flexi17 Replies
Altera_ForumIf you need delay lines, you design is probably flawed.
Why do you want one?- Altera_Forum
The delay line is there to support very small times, which can not be reached by synchronous design AFAIK. So, by delaying an edge through a delay line, I can get finer information.
- Altera_Forum
So I had a project where we actually had a need to do this. Nowdays the IO actually has dynamically programmable delay elements.
However, you essentially need to connect a bunch of ALUTs in cascade. Then you need a mux or muxes (more ALUTs) to dynamically select which "tap" you want. You can also allow dynamically bypass ALUTs in the cascade. In order for this to work you have to control the placement of each ALUT so as to keep your design reproducable. Then the final step ... characterize. You'll have to try the various permutations of your selections to see what delays you get. In our case exact delay was not required as we merely need statistical coverage of delays. - Altera_Forum--- Quote Start --- The delay line is there to support very small times, which can not be reached by synchronous design AFAIK. So, by delaying an edge through a delay line, I can get finer information. --- Quote End --- what kind of information. You still havent said what the purpose is.
- Altera_Forum
The delay line is there to fill the gap: when I want to measure a signal, let's say a 1pps-signal, but not with a clock of 100 MHz, but 1GHz or higher, I can delay the 1pps signal and find out when the clock fits the delay. Is it now clear?
- Altera_Forum
FPGA internal fabric is not designed to run with signals that run at GHz speed. Delays using ALUTs are normally only to scew a signal at an output or input put, not internally. If the input signal is running at GHz speeds, you will need to use one of the high speed GX transeivers (available on GX FPGAs), and maybe an associated IP core.
I dont think you'll be able to do what you want using the normal internals of an FPGA. - Altera_Forum
The signals that I process are not at GHz, but the times measured should be below 1 ns. The signals are quite slow (1 pulse per second)
I think, that the FPGA could be used to make a delay, as I could do this using hardware inverters. Why does this not work? - Altera_Forum
I dont quite understand what you're measuring. Is it the length of the pulse?
- Altera_Forum
yes, I want to measure the length of the 1pps signal, but more precise than with 100MHz.
- Altera_Forum
There are various previous threads related to implementing logic cell delays.
http://www.alteraforum.com/forum/showthread.php?t=27284 http://www.alteraforum.com/forum/showthread.php?t=19328 Apart from general PVT (process, voltage, temperature) variations affecting the accuracy of logic cell delays, there are some specific problems that make it unlikely to get uniform delay steps in the design. It's mainly due to the core and routing resources structure and the way, how they are handled by the place and route tool.
