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Altera_Forum's avatar
Altera_Forum
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14 years ago

Delay chain design?

Hi I am using the cycloneIII 3c120 kit to learn designing with FPGA. What I would like to do is a delay chain, in which a signal is delayed by each chain element on the order of 100..500ps...
Altera_Forum's avatar
Altera_Forum
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14 years ago

The delay line is there to support very small times, which can not be reached by synchronous design AFAIK. So, by delaying an edge through a delay line, I can get finer information.