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Altera_Forum's avatar
Altera_Forum
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14 years ago

Delay chain design?

Hi I am using the cycloneIII 3c120 kit to learn designing with FPGA. What I would like to do is a delay chain, in which a signal is delayed by each chain element on the order of 100..500ps...
Altera_Forum's avatar
Altera_Forum
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14 years ago

FPGA internal fabric is not designed to run with signals that run at GHz speed. Delays using ALUTs are normally only to scew a signal at an output or input put, not internally. If the input signal is running at GHz speeds, you will need to use one of the high speed GX transeivers (available on GX FPGAs), and maybe an associated IP core.

I dont think you'll be able to do what you want using the normal internals of an FPGA.