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Altera_Forum
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14 years ago

Delay chain design?

Hi I am using the cycloneIII 3c120 kit to learn designing with FPGA. What I would like to do is a delay chain, in which a signal is delayed by each chain element on the order of 100..500ps...
Altera_Forum's avatar
Altera_Forum
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14 years ago

There are various previous threads related to implementing logic cell delays.

http://www.alteraforum.com/forum/showthread.php?t=27284

http://www.alteraforum.com/forum/showthread.php?t=19328

Apart from general PVT (process, voltage, temperature) variations affecting the accuracy of logic cell delays, there are some specific problems that make it unlikely to get uniform delay steps in the design. It's mainly due to the core and routing resources structure and the way, how they are handled by the place and route tool.