DDR3 Write Leveling and Read Calibration

Question

Hello,

I was told to repost my enquiry, so I am doing that. I am creating my own DDR3 controller. It is coming along well, but I have hit a few snags. My initialization up to and including the ZQ calibration is done. The issue then becomes trying to ensure that my write leveling and read calibration are correct. I have them both written, but I am not confident in them. Does anyone have any examples? The Jedec standard for DDR3 is free to download and is also on github. I have used the standards, but the write leveling is not very well written. I use VHDL and my chip is a DDR3-1600 one. My code is attached below.

Thank you,

Drew

adzimzm_altera · Answer

Hello Drew,Thank you for submitting your question in Intel Community.Based on your question, you are developing the DDR3 memory controller and currently facing some issues on the calibration stages.Unfortunately, I cannot support to review your memory controller code in this thread.Because of that I will transfer this thread to community support.Regards,Adzim

matrix7878 · Answer

Hello,     Yes, I am writing a controller for DDR3 memory and would like to know how the write calibration and read leveling can be implemented.  Thank you for transferring it to the community.Drew

matrix7878 · Answer

Hello,     No one has responded to me with a solution.  Is it possible to have an Intel Engineer help me?Thank you,Drew

fvm · Answer

Hi,DDR3 external memory interface with write leveling needs clock fine delay, e.g. implemented by a delay chain, see e.g. https://cdrdv2-public.intel.com/666668/emi_ip-683841-666668.pdfI don't recognize a similar feature in your code.

matrix7878 · Answer

Hello,

That is what I am trying to figure out. If I can get an example code, or something similar to how to do it without an IP, that would be great. I can figure out the delays then when the actual logic is written.

Thank you

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DDR3 Write Leveling and Read Calibration

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