Forum Discussion

Occasional Contributor

1 year ago

DDR3 Write Leveling and Read Calibration

Hello, I was told to repost my enquiry, so I am doing that. I am creating my own DDR3 controller. It is coming along well, but I have hit a few snags. My initialization up to and includin...

ddr3.vhd14 KB

Board Debug

Configuration

Programmable Logic Device

MATRIX7878

Occasional Contributor

1 year ago

Hello,

No one has responded to me with a solution. Is it possible to have an Intel Engineer help me?

Thank you,

Drew

FvM

Super Contributor

1 year ago

Hi,
DDR3 external memory interface with write leveling needs clock fine delay, e.g. implemented by a delay chain, see e.g. https://cdrdv2-public.intel.com/666668/emi_ip-683841-666668.pdf
I don't recognize a similar feature in your code.

Forum Discussion

DDR3 Write Leveling and Read Calibration

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