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GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

DDR MT46V16M16P-5B on cycloneIV EP4CE6

Good morning.
I would like to use a Micron MT46V16M16TG-6T model sdram on an intel cycloneIV ep4ce6e22c8 144-pin EQFP.
This DDR SDRAM is included in the "DDR High Performance Controller v18.1" megawizard list.
This DDR has 2pin "DM" (data_mask), 16 "DQ" lines, and 2 "DQS" lines.
Instead the cyclone IV ep4ce6e22c8 144-pin EQFP has only 2 Numbers
× 8 Groups (I attach photos).



However, the fitter is set to use 2 x9 Groups banks, as it tries to use the 2 DM 
pins (data_mask) as well.



Are the data_mask signals mandatory?
Is there a quartus prime way to set them out of the 8 pin DQ group?



Is it possible not to use them at all and on the ddr force them to '0'?

Best regards, Luca.
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi Luca,


    Yes you can set the "Total Memory interface DQ width" to 16 bits and disable the "Drive DM pins from FPGA" option.


    I hope you can understand the memory parameter setting.

    Do let me know if you have any further question on this thread.


    Regards,

    Adzim


7 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Luca,


    Thank you for submitting your question in Intel Community.

    I'm Adzim from Penang Global Application Engineer.

    I will assist you in this thread.


    The DM pin is required when writing to DDR2 and DDR SDRAM devices.


    You may set the DQ width of 8 by modifying the parameter of memory preset in the IP GUI.



    Regards,

    Adzim


    • LMelo2's avatar
      LMelo2
      Icon for New Contributor rankNew Contributor
      3 years ago

      Thanks for the reply.

      Now i write this reply with my second Intel account (LMelo2).

      The setting you suggest is actually the one already present by default.

      However, the megawizard has another setting, "DRIVE DM PIN FOR FGA".

      But if set "NO" this option, the DM pins [1: 0] are not generated.

      In this case is it sufficient to connect the DMs directly on the DDR to '0'?

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Luca,

    In my previous reply, the parameter can be found as snapshot below.

    Then you will have one DQ group only.

    If the "Drive DM pins for FPGA" is set to no, then you're not using the DM pin in the design.

    You will have a x8 DQ group in the design.

    Regards,

    Adzim

    • GOMEZ_IT's avatar
      GOMEZ_IT
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      OK understood. But in case you say I am forced to work with 8 bits on the ram, and not with 16 bits. Is there any way to work at 16bit DQ and not use the 2 bit DM (data mask)?

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Luca,


    Yes you can set the "Total Memory interface DQ width" to 16 bits and disable the "Drive DM pins from FPGA" option.


    I hope you can understand the memory parameter setting.

    Do let me know if you have any further question on this thread.


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Luca,


    I don't receive any further question on this thread. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Regards,

    Adzim