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GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

DDR MT46V16M16P-5B on cycloneIV EP4CE6

Good morning. I would like to use a Micron MT46V16M16TG-6T model sdram on an intel cycloneIV ep4ce6e22c8 144-pin EQFP. This DDR SDRAM is included in the "DDR High Performance Controller v18.1" megawi...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi Luca,


    Yes you can set the "Total Memory interface DQ width" to 16 bits and disable the "Drive DM pins from FPGA" option.


    I hope you can understand the memory parameter setting.

    Do let me know if you have any further question on this thread.


    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Luca,


Thank you for submitting your question in Intel Community.

I'm Adzim from Penang Global Application Engineer.

I will assist you in this thread.


The DM pin is required when writing to DDR2 and DDR SDRAM devices.


You may set the DQ width of 8 by modifying the parameter of memory preset in the IP GUI.



Regards,

Adzim


LMelo2's avatar
LMelo2
Icon for New Contributor rankNew Contributor
3 years ago

Thanks for the reply.

Now i write this reply with my second Intel account (LMelo2).

The setting you suggest is actually the one already present by default.

However, the megawizard has another setting, "DRIVE DM PIN FOR FGA".

But if set "NO" this option, the DM pins [1: 0] are not generated.

In this case is it sufficient to connect the DMs directly on the DDR to '0'?