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GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

DDR MT46V16M16P-5B on cycloneIV EP4CE6

Good morning. I would like to use a Micron MT46V16M16TG-6T model sdram on an intel cycloneIV ep4ce6e22c8 144-pin EQFP. This DDR SDRAM is included in the "DDR High Performance Controller v18.1" megawi...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    3 years ago

    Hi Luca,


    Yes you can set the "Total Memory interface DQ width" to 16 bits and disable the "Drive DM pins from FPGA" option.


    I hope you can understand the memory parameter setting.

    Do let me know if you have any further question on this thread.


    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Luca,


I don't receive any further question on this thread. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Regards,

Adzim