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Honored ContributorDC offset removal using FPGA?
I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it?
Also, i need guidence regarding the DC removal.I have studied about it but got nothing as a final conclusion that whether to apply a HPF or LPF and then a subtractor. Please provide help required urjectly.23 Replies
Altera_Forum--- Quote Start --- Maybe you can make me clear whether the AC couple of the differential ADC just eliminate the DC (or noise) of the signal source, but there also is intrinsic DC of the ADC devices? --- Quote End --- AC coupling just breaks the DC path from the signal source to the ADC pins. The DC value on the ADC pins is then determined by the ADC. Ideally the ADC manufacturer designed the part so that it defaults to a DC level that corresponds to the mid-range of the ADC output codes. However, there is no guarantee of that, so you have to check. For example, I have used ADCs with track-and-hold DC offset control, so that you can adjust the DC level of an AC coupled ADC. Cheers, Dave- Altera_Forum
Hi DWH,
Maybe you can make me clear whether the AC couple of the differential ADC just eliminate the DC (or noise) of the signal source, but there also is intrinsic DC of the ADC devices? - Altera_Forum
Dear DWH： I must show my thanks for your kindly help！ Ｉthink I would have more questions. I'll come back if I don't deal with. Thanks again! Jerry
- Altera_Forum
Hi Jerry,
--- Quote Start --- We used AC couple for our system, but there is still DC inside FPGA after ADC sampling without any signal feeding, why? --- Quote End --- DC appears due to the asymmetries in the ADCs quantization transfer function. The conversion from analog voltage to a digital code is ideally a linear 'staircase' with each code converting an equivalent width of voltages. Practical ADCs have varying widths, and so some code bins end up with more samples than they really should, and others have less. The DC value of the digital signal it is mean, or expected value, and the expected value is <x> = sum_n w[n]P[n] where w[n] is the output weight (binary code) and P[n] is the probability of that code, i.e., the histogram bar height normalized by the number of samples. The histogram bar heights for a symmetric input, eg. a sine wave, have symmetry in the P[n], but when you have non-linear threshold voltages, the P[n] change heights, and this results in <x> having a non-zero value, i.e., a mean or DC offset. The attached document has a more detailed explanation. Look at the noise source figures, and you'll see DC created by the threshold non-linearities. Note that you will also get DC if you do your rounding wrong, i.e., if you use truncation. See the slides in this talk for an example of that (p41 of the PDF, p40 on the slide); http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf) Cheers, Dave - Altera_Forum
Hello researcher_123 (http://www.alteraforum.com/forum/member.php?u=51541):
Why don't you use histogram and get the DC value? Hello Dave: We used AC couple for our system, but there is still DC inside FPGA after ADC sampling without any signal feeding, why? Thanks Jerry - Altera_Forum--- Quote Start --- the signal i have is such that at the start of the samples, i have some data i need to ignore, but somewhere in the middle i have the desired data which i need to analyze, does this give some information about what type of filter (bandpass, lowpass or highpass) to be used? --- Quote End --- No, but it complicates your design. How many samples will you have in a continuous block? And how many coefficients will you have in your filter? You may need to have a state machine that allows the filter to fill with valid samples before you consider the output of the filter valid. What you describe is not unusual though. I have digital filters with outputs that have to be ignored for a few microseconds every millisecond, due to a local oscillator being changed. In my case, the logic processing the output of the digital filter is disabled and then re-enabled. Cheers, Dave
- Altera_Forum
Filters do their filtering job in the frequency domain. Filters as such cannot selectively remove samples from time domain signal but you can either ignore initial stream as it is washed away or discard these samples through logic. Most receivers need time to lock and several msec of data are washed away before they make use of received data.
- Altera_Forum
i have a question, the signal i have is such that at the start of the samples, i have some data i need to ignore, but somewhere in the middle i have the desired data which i need to analyze, does this give some information about what type of filter (bandpass, lowpass or highpass) to be used?
- Altera_Forum
Thankyou Dave, i think i am kind of doing it well. I will surely be back with some questions .
- Altera_Forum--- Quote Start --- Do u mean that the tap delay which is infact the number of coefficients will be equal to the number of samples we have at the imput? --- Quote End --- For a simple implementation of an FIR filter with N taps, you will have N-1 registers that are clocked at the same rate as the ADC. You will have N-input samples from the ADC inside the delay line of the FIR filter (one at the input, and (N-1) in the registers) at any point in time. So you will have an equal number of samples as coefficients inside the FPGA. Cheers, Dave
