DC offset removal using FPGA?

See my post at:

http://www.alteraforum.com/forum/showthread.php?t=29991&highlight=dc+filtering&page=2

you filter your data when parallelised into readable samples.

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I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it?

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Can you control the DC offset in the analog domain? If so, it would be better to eliminate it there, as then you can use the full dynamic range of your ADC.

Where is this DC coming from? If your ADC is AC-coupled, then the DC could be due to a bad input offset voltage, which some ADCs provide controls to eliminate. If your ADC is DC coupled, then you need to decide why its DC coupled, and decide if you want to change to AC coupling for your current application.

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Also, i need guidence regarding the DC removal.I have studied about it but got nothing as a final conclusion that whether to apply a HPF or LPF and then a subtractor.

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What is the signal you are trying to measure?

If you are digitally demodulating your signal and then filtering it, its quite possible your digital filter will be sufficient to remove the DC. Whether this would be sufficient, depends on how much DC is getting into your system, i.e., if you have a huge DC spike, then your filter stop-band rejection might need to be very high to remove it.

You can also use the methods Kaz suggests in the thread he references, or a combination of DC removal filter, followed by digital demodulation and further filtering.

Cheers,

Dave

I understand the method provided by Kaz, i think. But i lag the connection of how do we implement this DC filter using FPGAs, as this would would be my first attempt to try some DSP usinf FPGAs.

I have data from a transducer and it is being passed through ADc and then deserialized.

I will check for the DC and AC coupling.

But if i am right, i need to simulate this model using matlab to atleast figure out the basics of how moving average filter works.

Thankx

Also, why are IIR recommended, can we use FIR too?

I would be thankful for any help in form of any manuals or tutorials for implementation of these concepts in equivalent verilog (FPGA) domain?

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why are IIR recommended, can we use FIR too?

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Either will work. Ultimately it comes down to filter performance versus FPGA resources; IIRs can be more efficient, but they can have issues with stability and phase non-linearity, however, these issues can be overcome.

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I would be thankful for any help in form of any manuals or tutorials for implementation of these concepts in equivalent verilog (FPGA) domain?

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Here's a tutorial you can look at, with associated VHDL

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.zip)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip)

Cheers,

Dave

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But if i am right, i need to simulate this model using matlab to atleast figure out the basics of how moving average filter works.

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Simulation using MATLAB is a good approach. The slides have an example of a moving average filter, and an FIR filter. The main difference between a moving average filter and a FIR filter is (potentially) a scaling factor.

For example, a 4-point moving average filter is simply the average of 4-samples

y[m] = 1/4*sum_{n=0}{n=3} x[m-n]

whereas a 4-coefficient FIR filter is

y[m] = sum_{n=0}{n=3} h[n]x[m-n]

If h[n] = 1/4, then the two are the same. However, there is really no need to have 1/4 for each coefficient, as they can all be 1, and the final sum can be right-shifted by 2-bits to perform the divide by 4. This essentially gets you back to the moving average equation.

A moving average filter is a pretty simple filter. It might not be appropriate for your application, but it will help you understand filters, so go ahead and simulate it in both MATLAB and Modelsim.

Cheers,

Dave

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Thank you for the material, i will look into it in detail and will try doing some matlab testing. I think i will start up with some IIR filter. Will any type of IIR filter work fine?

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No, IIR filters will not just work fine.

If you are just starting to learn about filters. Learn about FIR first.

In MATLAB, there are z-transform analysis tools that will help you plot the poles and zeros of IIR filters. These plots must be used to confirm the stability of the quantized filter response. (Don't worry if these words are meaningless to you at the moment - but at least now you know what words to look for.).

Cheers,

Dave

hi, i just went through the slides and studied the handouts for implementations. The thing i am confused is that there are mentioned three things for a digital filter:

-an adder

- a multiplier

- a delay element

these are definitely there due to the impulse responses.

NOTE: i am just studying and talkign about FIR filters at the moment.

I have two questions if someone could clarify:

1- How to we decide the tap delay? If i have a signals, at what factor is it dependent?

2- How do i figure out the co-efficients or the multiplication values for the impulse response.

As the filter coefficients in my case are most important as they provide me with the amount of weightage given to each delayed element.

Please clarigy?

ALso please verify:

the sampling frequency fs used in the FIR filter is the same which would be used by the ADC for sampling?