CycloneV's Altera PLL V13.1 simulation problem

What clock frequency are you generating out of the PLL? If it's 'too high' I suspect the cut down version of ModelSim included with the Web Edition of Quartus won't simulate it.

This is indicative of behaviour I've seen when using PLLs generated for Cyclone IV devices (ALTPLL). It would quite happily simulate with output frequencies below 100MHz, but not over...

Hi a_x_h_75,

Thank you very much for your comment.

Oscillator of this board is 50MHz and output of my PLLs are 100MHz and 400MHz (use 2 PLLs).

I'll try scaling down my system clocks and simulate, after that I will post result here.

Hi a_x_h_75 and FvM,

Have tried both of your comment but still not work.

I suspected that there's may something wrong about my sim library.

Below are warning displayed from my modelsim.

Have you ever seen warning like this before ?

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# Loading cyclone5_pll.testbench(behavioral)

# Loading cyclone5_pll.top(behavioral)

# Loading cyclone5_pll.pll(rtl)

# ** Warning: (vsim-3473) Component instance "pll_inst : PLL_0002" is not bound.

# Time: 0 ps Iteration: 0 Instance: /testbench/MODULE_TOP/PLL_MODULE File: E:/xxx/xxx/xxx/project/cyclone_5_pll_sim/ipmodule/PLL.vhd

# ** Warning: (vsim-8684) No drivers exist on out port /testbench/MODULE_TOP/PLL_MODULE/outclk_0, and its initial value is not used.

#

# Therefore, simulation behavior may occur that is not in compliance with

#

# the VHDL standard as the initial values come from the base signal /testbench/MODULE_TOP/wCLKOUT.

#

# ** Warning: (vsim-8684) No drivers exist on out port /testbench/MODULE_TOP/PLL_MODULE/locked, and its initial value is not used.

#

# Therefore, simulation behavior may occur that is not in compliance with

#

# the VHDL standard as the initial values come from the base signal /testbench/MODULE_TOP/wLOCK.

#

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Hi,

I finally understood that only vhdl file created by quartus is not enough.

I needed to include one more module hiden inside a folder (PLL_0002) into a project as well.

By doing this, warnings seems to be disappear but now I'm facing a new problem.

It's appear that modelsim (free version) can only simulate one hdl language at a time, which my code is in vhdl while PLL_0002 module is in verilog. !!!

Can anyone confirm that it is true or not ?

You guys have no problem with mixed-language simulation means you are coding in verilog or using licensed version, haven't you ?

Below is my latest warning message.

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# ALTERA version supports only a single HDL

# ** Error: (vsim-3039) E:/xxx/xxx/xxx/project/cyclone_5_pll_sim/vhdl/top.vhd(38): Instantiation of 'PLL_0002' failed.

---------------------------------------------------------------------------------------------------------

Hi!

I have the same problem. Have you find a solution to this problem?

Bump,

Having the same problem trying to simulate pll with pll reconfig megafunctions. Have attached example project which when compiled and simulated with modelsim-altera getting the same issues. Attempted with Arriav device rather than Cyclonev and get the same issues.

I am using quartus sub edition 13.1 with windows 7 64bit modelsim altera 10.1d

Reading on the internet it seems like it might be a library issue in that some extra libraries need compiling (or just dont work!) but I havent been able to find anything that worked.

I am completely stuck so hope someone else has some ideas!

Hello Kurukuru,

For your information I had a problem with Altera PLL on cyclone V E when I applied the last update on Quartus 13.1. I did not manage to simulate the PLL with modelsim so I removed the update and that's working now. I think you can write a Support Ticket on this topic.

Regards,