Altera_ForumHonored Contributor12 years agoCycloneV's Altera PLL V13.1 simulation problem Hi, I'm using Altera SOCkit (CycloneV) and generated altera pll v13.1 using quartus v13.1.0.162 web edition + latest patch. Now I'm trying to simulate the generated pll using modelsim but ...Show More
Altera_ForumHonored Contributor12 years agoTo simulate PLLs, Modelsim time resolution must be changed from default 1 ns to 1 ps.
Recent DiscussionsPart Status requestAgilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation DiscrepancyVcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0Arria 10: Remote Update Factory Fallback won't work & Watchdog does not triggerIBIS models GTS banks agilex 5E