CycloneV's Altera PLL V13.1 simulation problem

Hi,

I finally understood that only vhdl file created by quartus is not enough.

I needed to include one more module hiden inside a folder (PLL_0002) into a project as well.

By doing this, warnings seems to be disappear but now I'm facing a new problem.

It's appear that modelsim (free version) can only simulate one hdl language at a time, which my code is in vhdl while PLL_0002 module is in verilog. !!!

Can anyone confirm that it is true or not ?

You guys have no problem with mixed-language simulation means you are coding in verilog or using licensed version, haven't you ?

Below is my latest warning message.

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# ALTERA version supports only a single HDL

# ** Error: (vsim-3039) E:/xxx/xxx/xxx/project/cyclone_5_pll_sim/vhdl/top.vhd(38): Instantiation of 'PLL_0002' failed.

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