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jonathanb17's avatar
jonathanb17
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1 month ago
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[CycloneV SX] LVDS IO datarate

Hi,

I am trying to interface a Cyclone V SX (DE10 standard) with a 500MSPs DAC (AD9783). The DAC uses 17 x LVDS DDR parallel inputs. The double datarate is used by the DAC to take 2x  So I set up the FPGA outputs to LVDS standard (2.5V), and using the alt_ddio megafunction. The timing constraints for the clock is set to 500MHz. However, the timing analyzer tells me that the maximum achievable datarate is 275MHz.

From what I have gathered here, the FPGA should be able to sustain a datarate of 640Mbps only using the softcore.

 

My simple question is : Is the LVDS maximum datarate only achievable when using the LVDS Softcore?  

Thank you for your answer. 

Generic Io
  • FvM's avatar
    FvM
    1 month ago

    Hi,

    I'm not completely sure about your design parameters, but AD9783 interface with 500 MHz DAC clock is actually using 2x500 MSPS LVDS Data rate, because the data stream involves I and Q data.

    Cyclone V isn't able to handle LVDS with 500 MHz DDR clock and 1000 MSPS.

    Regards Frank

5 Replies

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi,

     

    Yes, it is correct, Cyclone V SX can't reliably sustain 500 MHz DDR LVDS using DDIO registers. Furthermore, the 640Mbps figure in the documentation applies to dedicated LVDS SERDES channels. However, even using the dedicated LVDS SERDES blocks, Cyclone V maximum at 840Mbps/channel, is still below the AD9783 effective 1000MSPS.

     

    So, using bus widening (SERDES factor 4) to lower the internal clock rate while maintaining throughput is the suggested alternative, and it requires devices that support SERDES factor up to x8 and more than 1Gbps/channel. I confirmed from the datasheet of Cyclone 10 GX, Arria 10 GX, and Agilex 3/5, they can meet the requirements.

     

    Regards,
    Aqid

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    Hi Jonathan,

    Cyclone 10 GX, Arria 10 GX or Agilex 3/5 can handle the data rate. They also can't use SERDES factor 2 (simple DDR register) because the resulting core data rate of 500 MHz for I and Q would be too high. Need to use e.g. SERDES factor 4 and core data rate of 250 MHz with doubled data width.

    Regards
    Frank 

  • jonathanb17's avatar
    jonathanb17
    Icon for New Contributor rankNew Contributor
    1 month ago

    Thank you for your reply. 

    I am checking for another solution. 

    Best regards,

    Jonathan

    • AqidAyman_Altera's avatar
      AqidAyman_Altera
      Icon for Regular Contributor rankRegular Contributor
      30 days ago

      Dear Customer,

      I will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

      Thank you for engaging with us!

      Best regards,
      Altera Technical Support

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    Hi,

    I'm not completely sure about your design parameters, but AD9783 interface with 500 MHz DAC clock is actually using 2x500 MSPS LVDS Data rate, because the data stream involves I and Q data.

    Cyclone V isn't able to handle LVDS with 500 MHz DDR clock and 1000 MSPS.

    Regards Frank