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jonathanb17's avatar
jonathanb17
Icon for New Contributor rankNew Contributor
1 month ago
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[CycloneV SX] LVDS IO datarate

Hi, I am trying to interface a Cyclone V SX (DE10 standard) with a 500MSPs DAC (AD9783). The DAC uses 17 x LVDS DDR parallel inputs. The double datarate is used by the DAC to take 2x  So I set up th...
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  • FvM's avatar
    FvM
    1 month ago

    Hi,

    I'm not completely sure about your design parameters, but AD9783 interface with 500 MHz DAC clock is actually using 2x500 MSPS LVDS Data rate, because the data stream involves I and Q data.

    Cyclone V isn't able to handle LVDS with 500 MHz DDR clock and 1000 MSPS.

    Regards Frank

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Hi,

 

Yes, it is correct, Cyclone V SX can't reliably sustain 500 MHz DDR LVDS using DDIO registers. Furthermore, the 640Mbps figure in the documentation applies to dedicated LVDS SERDES channels. However, even using the dedicated LVDS SERDES blocks, Cyclone V maximum at 840Mbps/channel, is still below the AD9783 effective 1000MSPS.

 

So, using bus widening (SERDES factor 4) to lower the internal clock rate while maintaining throughput is the suggested alternative, and it requires devices that support SERDES factor up to x8 and more than 1Gbps/channel. I confirmed from the datasheet of Cyclone 10 GX, Arria 10 GX, and Agilex 3/5, they can meet the requirements.

 

Regards,
Aqid