Forum Discussion

jonathanb17's avatar
jonathanb17
Icon for New Contributor rankNew Contributor
8 months ago
Solved

[CycloneV SX] LVDS IO datarate

Hi, I am trying to interface a Cyclone V SX (DE10 standard) with a 500MSPs DAC (AD9783). The DAC uses 17 x LVDS DDR parallel inputs. The double datarate is used by the DAC to take 2x  So I set up th...
Generic Io
  • FvM's avatar
    FvM
    8 months ago

    Hi,

    I'm not completely sure about your design parameters, but AD9783 interface with 500 MHz DAC clock is actually using 2x500 MSPS LVDS Data rate, because the data stream involves I and Q data.

    Cyclone V isn't able to handle LVDS with 500 MHz DDR clock and 1000 MSPS.

    Regards Frank

jonathanb17's avatar
jonathanb17
Icon for New Contributor rankNew Contributor
8 months ago

Thank you for your reply. 

I am checking for another solution. 

Best regards,

Jonathan

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
8 months ago

Dear Customer,

I will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

Thank you for engaging with us!

Best regards,
Altera Technical Support