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jonathanb17's avatar
jonathanb17
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1 month ago
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[CycloneV SX] LVDS IO datarate

Hi, I am trying to interface a Cyclone V SX (DE10 standard) with a 500MSPs DAC (AD9783). The DAC uses 17 x LVDS DDR parallel inputs. The double datarate is used by the DAC to take 2x  So I set up th...
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  • FvM's avatar
    FvM
    1 month ago

    Hi,

    I'm not completely sure about your design parameters, but AD9783 interface with 500 MHz DAC clock is actually using 2x500 MSPS LVDS Data rate, because the data stream involves I and Q data.

    Cyclone V isn't able to handle LVDS with 500 MHz DDR clock and 1000 MSPS.

    Regards Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 month ago

Hi Jonathan,

Cyclone 10 GX, Arria 10 GX or Agilex 3/5 can handle the data rate. They also can't use SERDES factor 2 (simple DDR register) because the resulting core data rate of 500 MHz for I and Q would be too high. Need to use e.g. SERDES factor 4 and core data rate of 250 MHz with doubled data width.

Regards
Frank