cyclone5 gt and ddrin 400 Mhz for adc acquisition

Hi to hall.

I'm trying to connect an ADC (ads5263) to a FPGA (cyclone 5 GT dev board).

The ADC has for each channel (4 channels in total) 2 lvds outputs and a bit clock of 400 MHz DDR.

So working on 100MSPS 16 bits will 800Mbps x 2 outputs = 1.6 Gbps.

The bit clock (400 MHz DDR) is center-aligned with the data of the 2 outputs.

The Tsu and Th of the adc is respectively: 0.23ns and 0.31 ns.

Reading the various documents I calculated the max and min delays related to the launch of virtual clock (that is 90 degrees in advance with respect to the latch clock supplied from the ADC):

default_tsu (@ 400MHz DDR) = 0.625 ns.

default_th (@ 400MHz DDR) = 0.625 ns.

tmax = default_tsu - t_su (ADC) = 0.625 - 0.23 = 0.395ns

tmax = 0.395ns

tmin = - (default_h - t_h (ADC) = 0.625 - 0.31 = - (0.315ns)

tmin = -0.315ns

I set the input_delay as follows:

# ************************************************* *************# time information# ************************************************* *************

set_time_format -unit ns -decimal_places 3

# ************************************************* *************# create clock# ************************************************* *************

create_clock -name {adc_bit_clk} -period 2.500 [get_ports {adc_bit_clk}]

create_clock -name {launch_bit_clk} -period 2.500 -waveform {1.875 3.125}

# **************************************************************# set input delay# **************************************************************

set_input_delay -add_delay -clock { launch_bit_clk } -max 0.395 [get_ports {adc_ch* adc_frm_clk}]

set_input_delay -add_delay -clock { launch_bit_clk } -clock_fall -max 0.395 [get_ports {adc_ch* adc_frm_clk}]

set_input_delay -add_delay -clock { launch_bit_clk } -min -0.315 [get_ports {adc_ch* adc_frm_clk}]

set_input_delay -add_delay -clock { launch_bit_clk } -clock_fall -min -0.315 [get_ports {adc_ch* adc_frm_clk}]

# set false paths to remove irrelevant setup and hold analysis

set_false_path -fall_from [get_clocks launch_bit_clk] -rise_to [get_clocks {adc_bit_clk}]

-setup

set_false_path -rise_from [get_clocks launch_bit_clk] -fall_to [get_clocks {adc_bit_clk}]

-setup

set_false_path -fall_from [get_clocks launch_bit_clk] -fall_to [get_clocks {adc_bit_clk}]

-hold

set_false_path -rise_from [get_clocks launch_bit_clk] -rise_to [get_clocks {adc_bit_clk}]

-hold

All signals are lvds, optimizations fitter at most.

But unfortunately timequest analysis fails.

According to you experts, there is a way to capture the data from the adc ads5263 at 400Mhz DDR of cyclone 5, using megafunction alt_ddio?

I also enclose a list of the pin settings used on cyclone5 GT dev board:

set_global_assignment -name family "cyclone v"

set_global_assignment -name device 5cgtfd9e5f35c7

set_global_assignment -name top_level_entity top_adc_sample

set_global_assignment -name original_quartus_version 16.0.0

set_global_assignment -name project_creation_time_date "14:55:45 december 05, 2016"

set_global_assignment -name last_quartus_version 16.0.0

set_global_assignment -name project_output_directory output_files

set_global_assignment -name min_core_junction_temp 0

set_global_assignment -name max_core_junction_temp 85

set_global_assignment -name device_filter_pin_count 1152

set_global_assignment -name error_check_frequency_divisor 256

set_global_assignment -name eda_simulation_tool "modelsim (vhdl)"

set_global_assignment -name eda_time_scale "1 ps" -section_id eda_simulation

set_global_assignment -name eda_output_data_format vhdl -section_id eda_simulation

set_global_assignment -name vhdl_file top_adc_sample.vhd

set_global_assignment -name partition_netlist_type source -section_id top

set_global_assignment -name partition_fitter_preservation_level placement_and_routing -section_id top

set_global_assignment -name partition_color 16764057 -section_id top

set_instance_assignment -name global_signal off -to adc_frm_clk

set_global_assignment -name sdc_file adc_sample.sdc

set_global_assignment -name power_preset_cooling_solution "23 mm heat sink with 200 lfpm airflow"

set_global_assignment -name power_board_thermal_model "none (conservative)"

set_global_assignment -name qip_file ddio1.qip

set_global_assignment -name timequest_multicorner_analysis on

set_global_assignment -name disable_ocp_hw_eval on

set_location_assignment pin_h17 -to adc_bit_clk

set_instance_assignment -name io_standard lvds -to adc_bit_clk

set_instance_assignment -name input_termination differential -to adc_bit_clk

set_location_assignment pin_f17 -to adc_frm_clk

set_instance_assignment -name io_standard lvds -to adc_frm_clk

set_instance_assignment -name input_termination differential -to adc_frm_clk

set_location_assignment pin_m16 -to adc_ch1_a

set_instance_assignment -name io_standard lvds -to adc_ch1_a

set_instance_assignment -name input_termination differential -to adc_ch1_a

set_location_assignment pin_b8 -to adc_ch1_b

set_instance_assignment -name io_standard lvds -to adc_ch1_b

set_instance_assignment -name input_termination differential -to adc_ch1_b

set_location_assignment pin_h16 -to "adc_bit_clk(n)"

set_location_assignment pin_f16 -to "adc_frm_clk(n)"

set_location_assignment pin_l17 -to "adc_ch1_a(n)"

set_location_assignment pin_a8 -to "adc_ch1_b(n)"

set_global_assignment -name optimization_mode "aggressive performance"

set_instance_assignment -name global_signal off -to adc_ch1_b

set_instance_assignment -name global_signal off -to adc_ch1_a

set_global_assignment -name optimize_multi_corner_timing off

set_global_assignment -name io_placement_optimization on

set_instance_assignment -name partition_hierarchy root_partition -to | -section_id top

Best regards.