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Honored Contributor
Honored Contributorcyclone5 gt and ddrin 400 Mhz for adc acquisition
Hi to hall. I'm trying to connect an ADC (ads5263) to a FPGA (cyclone 5 GT dev board). The ADC has for each channel (4 channels in total) 2 lvds outputs and a bit clock of 400 MHz DDR. So w...
Altera_ForumHonored Contributor
Honored ContributorNo way with ddio_in function.
I can respect the timequest analysis only if i use the lvdsrx megafunction, using the true lvds receivers of cyclone5. Best regards
