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Hi,
In my opinion you have entered wrong false path exceptions. You are saying that data is launched by rising edge of virtual clock LAUNCH_BIT_CLK (which is phase shifted +90 deg.), this means that you are latching data with falling edge of ADC_BIT_CLK. So you have to cut paths between same edge transfers in setup and between different edge transfers in hold.
Also I think you should use PLL in your design, which will help to meet timing in your design.
Regards.
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Hi vlrean!
My false path exceptions, I think they are correct (see image).
The launch is at rising and the latching is at rising.
Then the false path is from rising to falling for setup (et vice-versa), and from rising to rising(and falling to falling) for hold.
do you agree?
Honored Contributor
