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Honored Contributor
Honored Contributorcyclone5 gt and ddrin 400 Mhz for adc acquisition
Hi to hall. I'm trying to connect an ADC (ads5263) to a FPGA (cyclone 5 GT dev board). The ADC has for each channel (4 channels in total) 2 lvds outputs and a bit clock of 400 MHz DDR. So w...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi, In my opinion you have entered wrong false path exceptions. You are saying that data is launched by rising edge of virtual clock LAUNCH_BIT_CLK (which is phase shifted +90 deg.), this means that you are latching data with falling edge of ADC_BIT_CLK. So you have to cut paths between same edge transfers in setup and between different edge transfers in hold. Also I think you should use PLL in your design, which will help to meet timing in your design. Regards. --- Quote End --- Hi vlrean! My false path exceptions, I think they are correct (see image). The launch is at rising and the latching is at rising. Then the false path is from rising to falling for setup (et vice-versa), and from rising to rising(and falling to falling) for hold. do you agree?
