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Altera_Forum
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9 years ago

cyclone5 gt and ddrin 400 Mhz for adc acquisition

Hi to hall. I'm trying to connect an ADC (ads5263) to a FPGA (cyclone 5 GT dev board). The ADC has for each channel (4 channels in total) 2 lvds outputs and a bit clock of 400 MHz DDR. So w...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Hi,

No, i do not agree. You have wrong relationship between launch and latch clocks. See picture from datasheet :

https://www.alteraforum.com/forum/attachment.php?attachmentid=13019

Your relationship should look like:

https://www.alteraforum.com/forum/attachment.php?attachmentid=13020

Maybe I am wrong, this is from quick glance in to datasheet.

Correct your base and virtual clock constraints that they have correct relationship.

Correct false path exceptions and post your waveform from TimeQuest.