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BrianSune_Froum's avatar
BrianSune_Froum
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3 months ago
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Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations

Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specifi...
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Core Logic
Programmable Logic Device
  • CheepinC_altera's avatar
    CheepinC_altera
    21 days ago

    Hi Brian,

     

    Thank you for the update.

     

    Just to clarify, the legacy database I referred to is our internal database for legacy devices. Unfortunately, there is limited information available regarding this wrong data issue. Based on the available info, I believe it was originally initiated from a customer-reported case.

     

    You are also correct that the placement rules are enforced within Quartus. Since these rules are built into the tool, they cannot be overridden through a TCL command.

     

    I apologize for any inconvenience this may cause. 

BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
3 months ago

Dear Intel/Altera,

I want a neat answer:

For one side GXB confirmations: 3+3 bottom+up
When PCIe is used: What are the possible combination on Hard Core PCIe + custom GXB design.
Either CMU PLL or fPLL design on xN or x1.

I am a bit lost on the handbook.
TBH, reading it feels like it can configure as 6 but turns on the fitter does not.
So this is very puzzling.

Thanks,

Brian