Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations

Dear Intel/Altera,

I want a neat answer:

For one side GXB confirmations: 3+3 bottom+up
When PCIe is used: What are the possible combination on Hard Core PCIe + custom GXB design.
Either CMU PLL or fPLL design on xN or x1.

I am a bit lost on the handbook.
TBH, reading it feels like it can configure as 6 but turns on the fitter does not.
So this is very puzzling.

Thanks,

Brian