Honored ContributorWe want use pcie Configuration via Protocol, but we are confused with the pcie reset controller.
which pin can be used for pcie_npor_npor and pcie_npor_pin_perst? if use the CvP function, is it a must to use hard reset controller ? Please help!!!
Honored ContributorHi,
If I understand it correctly, the perst pin is dedicated pin available in the device. If you create the hard IP and let Fitter auto fit, it should select the dedicated pin.Honored ContributorThere is a dedicated HIP that support this CvP feature which is the bottom left HIP. Other HIP does not support CvP. For Cyclone V device, you need to use the nPERSTL1 for the reset controller. You can refer to the CVP user guide and Cyclone V PCIe user guides either in Avalon ST or Avalon MM from these links:
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cvp.pdf https://www.altera.com/en_us/pdfs/literature/ug/ug_c5_pcie_avst.pdf https://www.altera.com/en_us/pdfs/literature/ug/ug_c5_pcie_avmm.pdfHonored ContributorHi kerb,
Yes, if you use CvP function, is it a must to use hard reset controller. By default PCIe core is using hard reset controller.Honored ContributorYou could refer to https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cvp.pdf which mention about the need of hard reset controller. You may just search for the "hard reset controller" keyword in the document.
Honored ContributorI'm presently checking if CvP might be enabled in a Cyclone V GX PCIe design of 2012 by pure code redesign, of if hardware changes could be necessary.
--- Quote Start --- For Cyclone V device, you need to use the nPERSTL1 for the reset controller. --- Quote End --- That's in fact written in the CvP user guide. But the Cyclone V specific PCIe user guide tells: --- Quote Start --- • NPERSTL0: bottom left Hard IP and CvP blocks • NPERSTL1: top left Hard IP block • NPERSTR0: bottom right Hard IP block • NPERSTR1: top right Hard IP block For example, if you are using the Hard IP instance in the bottom left corner of the device, you must connect pin_perst to NPERSL0. For maximum use of the Cyclone V device, Altera recommends that you use the bottom left Hard IP first. This is the only location that supports CvP over a PCIe link. If your design does not require CvP, you may select other Hard IP blocks. --- Quote End --- This sounds more reasonable because NPERSTL0 is assigned to the bottom left PCIe hard IP incorporating the CVP function. It's also the configuration provided by the Altera Cyclone V GX FPGA Dev Kit. Unless someone can give a good explanation for the statement in the CvP user guide, I presume it's a typo. To ask a subsequent question, did somebody already implement CvP with Cyclone V GX and can comment about correctness of the documentation. Another simple question, I have been using Quartus 13.1 up to now, it tells me "CvP not supported for Cyclone V" when I try to enable it in the device configuration. Is it so that Cyclone V CvP requires Quartus 14 or did I anything (not obviously) wrong? Regards, FrankHonored ContributorThe info in CvP user guide "...use the nPERSTL1 for the reset controller." is correct.
The info in Cyclone V PCIe user guide ' NPERSTL0: bottom left Hard IP and CvP blocks" is a typo. The correction is " ' NPERSTL1: bottom left Hard IP and CvP blocks"" Please note that the NPERST mapping for Cyclone V is opposite for Stratix V and Arria V (where bottom HIP is associated with nPERSTL0, top HIP is associated with nPERSTL1). The correct mapping for Cyclone V is: TOP PCIe HIP --> nPERSTL0 BOTTOM PCIe HIP --> nPERSTL1Honored ContributorThanks for the clarifiction on the swap and typo.
Honored Contributor
